公开(公告)号：US06583491B1

公开(公告)日：2003-06-24

申请号：US10143162

申请日：2002-05-09

申请人： Chi-Feng Huang ,  Chun-Hon Chen

发明人： Chi-Feng Huang ,  Chun-Hon Chen

IPC分类号： H01L2900

CPC分类号： H01L28/55

摘要： Within a method for fabricating a microelectronic fabrication, and the microelectronic fabrication fabricated employing the method, there is formed within the microelectronic fabrication a capacitor structure upon a conductor stud layer formed into a first via defined by a patterned dielectric layer to reach a one of a pair of patterned conductor layers within the microelectronic fabrication prior to forming through the patterned dielectric layer a second via to reach the other of the pair of patterned conductor layers within the microelectronic fabrication. The method provides the resulting microelectronic fabrication with enhanced reliability and performance.

摘要翻译： 在制造微电子制造的方法和使用该方法制造的微电子制造中，在微电子制造中形成电容器结构，该电容器结构形成在由图案化的介电层限定的第一通孔中的导体柱层上，以达到 在微电子制造之前，在通过图案化的电介质层形成第二通孔以达到微电子制造中的一对图案化导体层中的另一个之前，微电子制造中的一对图案化导体层。 该方法提供了所得的微电子制造，具有增强的可靠性和性能。

公开(公告)号：US07122878B2

公开(公告)日：2006-10-17

申请号：US11143229

申请日：2005-06-02

申请人： Chi-Feng Huang ,  Chun-Hon Chen ,  Shy Chy Wong ,  Chih Hsien Lin

发明人： Chi-Feng Huang ,  Chun-Hon Chen ,  Shy Chy Wong ,  Chih Hsien Lin

IPC分类号： H01L29/00

CPC分类号： H01L28/60 ,  H01L21/28568 ,  H01L21/3143 ,  H01L21/31608 ,  H01L21/31637 ,  H01L21/3185 ,  H01L21/76838 ,  H01L28/75

摘要： A new method is provided for the creation of a high-reliability metal capacitor as part of back-end processing. A first layer of metal interconnect is created, ac contact point is provided in the surface of the first layer of interconnect aligned with which a capacitor is to be created. A copper interconnect is formed overlying the contact point using TaN for the bottom plate, a high dielectric-constant dielectric material capacitor and using TaN for the top plate. The deposited layers are patterned and etched, a spacer layer is formed over sidewalls of the capacitor to prevent capacitor sidewall leakage. Top interconnect metal is then formed by first depositing a layer of etch stop material for further interconnection of the capacitor and the semiconductor devices provided in the underlying substrate.

摘要翻译： 提供了一种用于创建高可靠性金属电容器作为后端处理的一部分的新方法。 产生金属互连的第一层，在要与其形成电容器的第一互连层的表面上提供交流接触点。 使用用于底板的TaN，高介电常数介电材料电容器和使用TaN作为顶板，形成覆盖接触点的铜互连。 沉积的层被图案化和蚀刻，在电容器的侧壁上形成间隔层以防止电容器侧壁泄漏。 然后通过首先沉积一层蚀刻停止材料形成顶部互连金属，用于电容器和设置在下面的衬底中的半导体器件的进一步互连。

公开(公告)号：US06916722B2

公开(公告)日：2005-07-12

申请号：US10307617

申请日：2002-12-02

申请人： Chi-Feng Huang ,  Chun-Hon Chen ,  Shy-Chy Wong ,  Chih Hsien Lin

发明人： Chi-Feng Huang ,  Chun-Hon Chen ,  Shy-Chy Wong ,  Chih Hsien Lin

IPC分类号： H01L21/02 ,  H01L21/285 ,  H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L21/20

CPC分类号： H01L28/60 ,  H01L21/28568 ,  H01L21/3143 ,  H01L21/31608 ,  H01L21/31637 ,  H01L21/3185 ,  H01L21/76838 ,  H01L28/75

摘要： A new method is provided for the creation of a high-reliability metal capacitor as part of back-end processing. A first layer of metal interconnect is created, a contact point is provided in the surface of the first layer of interconnect aligned with which a capacitor is to be created. A copper interconnect is formed overlying the contact point using TaN for the bottom plate, a high dielectric-constant dielectric material capacitor and using TaN for the top plate. The deposited layers are patterned and etched, a spacer layer is formed over sidewalls of the capacitor to prevent capacitor sidewall leakage. Top interconnect metal is then formed by first depositing a layer of etch stop material for further interconnection of the capacitor and the semiconductor devices provided in the underlying substrate.

摘要翻译： 提供了一种用于创建高可靠性金属电容器作为后端处理的一部分的新方法。 产生第一层金属互连，在第一层互连层的表面上提供一个接触点，与其形成电容器。 使用用于底板的TaN，高介电常数介电材料电容器和使用TaN作为顶板，形成覆盖接触点的铜互连。 沉积的层被图案化和蚀刻，在电容器的侧壁上形成间隔层以防止电容器侧壁泄漏。 然后通过首先沉积一层蚀刻停止材料形成顶部互连金属，以便电容器和设置在下面的衬底中的半导体器件进一步互连。

公开(公告)号：US20050221575A1

公开(公告)日：2005-10-06

申请号：US11143229

申请日：2005-06-02

申请人： Chi-Feng Huang ,  Chun-Hon Chen ,  Shy-Chy Wong ,  Chih Lin

发明人： Chi-Feng Huang ,  Chun-Hon Chen ,  Shy-Chy Wong ,  Chih Lin

IPC分类号： H01L21/02 ,  H01L21/285 ,  H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/20

CPC分类号： H01L28/60 ,  H01L21/28568 ,  H01L21/3143 ,  H01L21/31608 ,  H01L21/31637 ,  H01L21/3185 ,  H01L21/76838 ,  H01L28/75

摘要： A new method is provided for the creation of a high-reliability metal capacitor as part of back-end processing. A first layer of metal interconnect is created, ac contact point is provided in the surface of the first layer of interconnect aligned with which a capacitor is to be created. A copper interconnect is formed overlying the contact point using TaN for the bottom plate, a high dielectric-constant dielectric material capacitor and using TaN for the top plate. The deposited layers are patterned and etched, a spacer layer is formed over sidewalls of the capacitor to prevent capacitor sidewall leakage. Top interconnect metal is then formed by first depositing a layer of etch stop material for further interconnection of the capacitor and the semiconductor devices provided in the underlying substrate.

摘要翻译： 提供了一种用于创建高可靠性金属电容器作为后端处理的一部分的新方法。 产生金属互连的第一层，在要与其形成电容器的第一互连层的表面上提供交流接触点。 使用用于底板的TaN，高介电常数介电材料电容器和使用TaN作为顶板，形成覆盖接触点的铜互连。 沉积的层被图案化和蚀刻，在电容器的侧壁上形成间隔层以防止电容器侧壁泄漏。 然后通过首先沉积一层蚀刻停止材料形成顶部互连金属，以便电容器和设置在下面的衬底中的半导体器件进一步互连。

公开(公告)号：US06734079B2

公开(公告)日：2004-05-11

申请号：US10170840

申请日：2002-06-13

申请人： Chi-Feng Huang ,  Shyh-Chyi Wang ,  Chih-Hsien Lin ,  Chun-Hon Chen ,  Tien-I Bao ,  Syun-Ming Jang

发明人： Chi-Feng Huang ,  Shyh-Chyi Wang ,  Chih-Hsien Lin ,  Chun-Hon Chen ,  Tien-I Bao ,  Syun-Ming Jang

IPC分类号： H01L2120

CPC分类号： H01L28/55 ,  Y10S438/945

摘要： Within a method for fabricating a microelectronic fabrication, and the microelectronic fabrication fabricated employing the method, there is formed within the microelectronic fabrication a capacitor structure which comprises a first capacitor plate layer having formed thereupon a capacitor dielectric layer in turn having formed thereupon a second capacitor plate layer, wherein each of the foregoing layers having an exposed sidewall to thus form a series of exposed sidewalls. The capacitor structure also comprises a silicon oxide dielectric layer formed passivating the series of exposed sidewalls of the first capacitor plate layer, the capacitor dielectric layer and the second capacitor plate layer a silicon oxide dielectric layer.

摘要翻译： 在制造微电子制造的方法和使用该方法制造的微电子制造中，在微电子制造中形成电容器结构，该电容器结构包括依次形成有电容器电介质层的第一电容器板层，其上形成有第二电容器 板层，其中每个前述层具有暴露的侧壁，从而形成一系列暴露的侧壁。 电容器结构还包括形成钝化第一电容器板层的一系列暴露的侧壁，电容器介电层和第二电容器板层的氧化硅介电层的氧化硅介电层。

公开(公告)号：US20140055526A1

公开(公告)日：2014-02-27

申请号：US13957501

申请日：2013-08-02

申请人： Ta-Wei Hsueh ,  Ying-Lun Chang ,  Hsien-Chung Tai ,  Yung-Lung Han ,  Chi-Feng Huang

发明人： Ta-Wei Hsueh ,  Ying-Lun Chang ,  Hsien-Chung Tai ,  Yung-Lung Han ,  Chi-Feng Huang

IPC分类号： B41J2/155

CPC分类号： B41J2/155 ,  B41J2/14145 ,  B41J2002/14459 ,  B41J2202/20

摘要： A page-width array printing device includes a page-width array printing mechanism including at least one page-width array printing module. The page-width array printing module includes a printing platform, a first page-width array printing unit and a second page-width array printing unit. The first page-width array printing unit includes a plurality of first inkjet cartridges. The second page-width array printing unit includes a plurality of second inkjet cartridges. The first page-width array printing unit and the second page-width array printing unit are in parallel with each other. The first inkjet cartridges and the second inkjet cartridges are staggered and independently and detachably disposed on the printing platform. Each of the first inkjet cartridges and the second inkjet cartridges includes an inkjet chip. The inkjet chip includes four ink supply channels and a plurality of nozzles so as to perform a monochromatic or polychromatic page-width array printing operation.

摘要翻译： 页宽阵列打印设备包括具有至少一个页宽阵列打印模块的页宽阵列打印机构。 页宽阵列打印模块包括打印平台，第一页宽阵列打印单元和第二页宽阵列打印单元。 第一页宽阵列印刷单元包括多个第一喷墨盒。 第二页宽阵列印刷单元包括多个第二喷墨盒。 第一页宽阵列打印单元和第二页宽阵列打印单元彼此并联。 第一喷墨墨盒和第二喷墨墨盒是交错的并且可独立且可拆卸地设置在打印平台上。 第一喷墨盒和第二喷墨盒中的每一个包括喷墨芯片。 喷墨芯片包括四个供墨通道和多个喷嘴，以执行单色或多色页宽阵列打印操作。

公开(公告)号：US20120293191A1

公开(公告)日：2012-11-22

申请号：US13111730

申请日：2011-05-19

申请人： Chia-Chung Chen ,  Chi-Feng Huang ,  Tse-Hua Lu

发明人： Chia-Chung Chen ,  Chi-Feng Huang ,  Tse-Hua Lu

IPC分类号： G01R27/08 ,  H01L27/105 ,  H01L21/66

CPC分类号： H01L27/092 ,  G01R27/08 ,  G01R31/02 ,  H01L22/14 ,  H01L22/34 ,  H01L27/0207 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/1087 ,  H01L29/7835

摘要： A method of determining the reliability of a high-voltage PMOS (HVPMOS) device includes determining a bulk resistance of the HVPMOS device, and evaluating the reliability of the HVPMOS device based on the bulk resistance.

摘要翻译： 确定高压PMOS（HVPMOS）器件的可靠性的方法包括确定HVPMOS器件的体电阻，以及基于体电阻来评估HVPMOS器件的可靠性。

公开(公告)号：US20100012701A1

公开(公告)日：2010-01-21

申请号：US12219353

申请日：2008-07-21

申请人： Chi-Feng Huang ,  I-Hui Liu ,  Chun-Hsien Chiang

发明人： Chi-Feng Huang ,  I-Hui Liu ,  Chun-Hsien Chiang

IPC分类号： B25C5/11 ,  B25C5/02

CPC分类号： B25C5/0207 ,  B25C5/0242

摘要： A stapler has a supporting base, a magazine assembly, a trigger assembly and a leg-flatting device. The trigger assembly has a trigger lever and a pushing element. The pushing element is mounted pivotally on the trigger lever with a pivot and has two pushing arms extending toward the supporting base. The leg-flatting device is mounted on the supporting base and has a sliding base, a moving base and an anvil element. The sliding base is slidably mounted on the supporting base and has a pushed segment corresponding to and selectively pushed by the pushing arms. The moving base is selectively blocked by the sliding base to keep the moving base from moving downwardly before the sliding base sliding relative to the supporting base and has an elongated hole. The anvil element is mounted in the elongated hole in the moving base.

摘要翻译： 订书机具有支撑底座，仓库组件，触发器组件和脚踏平板装置。 触发器组件具有触发杆和推动元件。 推动元件通过枢轴枢转地安装在触发杆上，并且具有朝向支撑基座延伸的两个推动臂。 腿部平坦装置安装在支撑基座上，具有滑动基座，移动基座和砧座元件。 滑动基座可滑动地安装在支撑基座上并且具有与推动臂相对应并且被推动臂选择性推动的推动部分。 移动基座由滑动基座选择性地阻挡，以在滑动基座相对于支撑基座滑动之前保持运动基座向下移动并且具有细长的孔。 砧座元件安装在移动底座中的长孔中。

公开(公告)号：US20080035909A1

公开(公告)日：2008-02-14

申请号：US11819175

申请日：2007-06-26

申请人： Chih-Feng Lu ,  Horng-Shyang Chen ,  Dong-Ming Yeh ,  Chi-Feng Huang ,  Tsung-Yi Tang ,  Jian-Jang Huang ,  Yen-Cheng Lu ,  Chih-Chung Yang ,  Jeng-Jie Huang ,  Yung-Sheng Chen

发明人： Chih-Feng Lu ,  Horng-Shyang Chen ,  Dong-Ming Yeh ,  Chi-Feng Huang ,  Tsung-Yi Tang ,  Jian-Jang Huang ,  Yen-Cheng Lu ,  Chih-Chung Yang ,  Jeng-Jie Huang ,  Yung-Sheng Chen

IPC分类号： H01L31/024 ,  H01L21/22 ,  H01L21/302

CPC分类号： H01L33/06 ,  B82Y20/00 ,  H01L33/32

摘要： A method for controlling the color contrast of a multi-wavelength light-emitting diode (LED) made according to the present invention is disclosed. The present invention includes at least the step of increasing the junction temperature of a multi-quantum-well LED, such that holes are distributed in a deeper quantum-well layer of the LED to increase luminous intensity of the deeper quantum-well layer, thereby controlling the relative intensity ratios of the multiple wavelengths emitted by the LED. The step of increasing junction temperature of the multi-quantum-well LED is achieved either by controlling resistance through modulating thickness of a p-type electrode layer of the LED or by modifying the mesa area size to control its relative heat radiation surface area.

摘要翻译： 公开了一种用于控制根据本发明制造的多波长发光二极管（LED）的颜色对比度的方法。 本发明至少包括提高多量子阱LED的结温的步骤，使得空穴分布在LED的较深量子阱层中以增加较深量子阱层的发光强度，由此 控制由LED发射的多个波长的相对强度比。 通过调节LED的p型电极层的厚度或通过改变台面面积尺寸来控制其相对的热辐射表面积来实现增加多量子阱LED的结温的步骤。

公开(公告)号：US09159802B2

公开(公告)日：2015-10-13

申请号：US13471270

申请日：2012-05-14

申请人： Chu-Fu Chen ,  Chia-Chung Chen ,  Chi-Feng Huang ,  Victor Chiang Liang

发明人： Chu-Fu Chen ,  Chia-Chung Chen ,  Chi-Feng Huang ,  Victor Chiang Liang

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/66

CPC分类号： H01L29/66492 ,  H01L21/28518 ,  H01L21/76897 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7835

摘要： A device includes a substrate, a gate dielectric over the substrate, and a gate electrode over the gate dielectric. A drain region and a source region are disposed on opposite sides of the gate electrode. Insulation regions are disposed in the substrate, wherein edges of the insulation regions are in contact with edges of the drain region and the source region. A dielectric mask includes a portion overlapping a first interface between the drain region and an adjoining portion of the insulation regions. A drain silicide region is disposed over the drain region, wherein an edge of the silicide region is substantially aligned to an edge of the first portion of the dielectric mask.

摘要翻译： 器件包括衬底，衬底上的栅极电介质，以及栅极电介质上的栅电极。 漏极区域和源极区域设置在栅电极的相对侧上。 绝缘区域设置在基板中，其中绝缘区域的边缘与漏极区域和源极区域的边缘接触。 介电掩模包括与漏极区域和绝缘区域的相邻部分之间的第一界面重叠的部分。 漏极硅化物区域设置在漏极区域之上，其中硅化物区域的边缘基本上与电介质掩模的第一部分的边缘对准。