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21 条记录 (耗时 0.066 秒)

    GENERATING AND AMPLIFYING DIFFERENTIAL SIGNALS
    2.
    发明申请
    GENERATING AND AMPLIFYING DIFFERENTIAL SIGNALS 有权
    生成和放大差分信号

    公开(公告)号：US20130010560A1

    公开(公告)日：2013-01-10

    申请号：US13535075

    申请日：2012-06-27

    申请人： Chung-Ji LU ,  Hung-Jen LIAO ,  Cheng Hung LEE ,  Derek C. TAO ,  Annie-Li-Keow LUM ,  Hong-Chen CHENG

    发明人： Chung-Ji LU ,  Hung-Jen LIAO ,  Cheng Hung LEE ,  Derek C. TAO ,  Annie-Li-Keow LUM ,  Hong-Chen CHENG

    IPC分类号： H03F3/45 ,  G11C7/06

    CPC分类号： G11C7/067 ,  G11C7/065

    摘要： A circuit includes a first node, a second node, a first current mirror circuit, and a second current minor circuit. The first current mirror circuit has a reference end and a mirrored end. The reference end of the first current minor circuit is coupled to the first node, and the mirrored end of the first current minor circuit is coupled to the second node. The second current minor circuit has a reference end and a mirrored end. The reference end of the second current minor circuit is coupled to the second node, and the mirrored end of the second current minor circuit is coupled to the first node.

    摘要翻译： 电路包括第一节点，第二节点，第一电流镜电路和第二电流次要电路。 第一电流镜电路具有参考端和镜像端。 第一当前次要电路的参考端耦合到第一节点，并且第一当前次要电路的镜像端耦合到第二节点。 第二个当前次级电路具有参考端和镜像端。 第二电流次级电路的参考端耦合到第二节点，并且第二电流次级电路的镜像端耦合到第一节点。

    SRAM CELLS, MEMORY CIRCUITS, SYSTEMS, AND FABRICATION METHODS THEREOF
    3.
    发明申请
    SRAM CELLS, MEMORY CIRCUITS, SYSTEMS, AND FABRICATION METHODS THEREOF 有权
    SRAM电池，存储器电路，系统及其制造方法

    公开(公告)号：US20130003445A1

    公开(公告)日：2013-01-03

    申请号：US13609930

    申请日：2012-09-11

    申请人： Cheng Hung LEE ,  Hung-Jen LIAO

    发明人： Cheng Hung LEE ,  Hung-Jen LIAO

    IPC分类号： G11C11/40 ,  H01L21/8244

    CPC分类号： G11C11/412

    摘要： A static random access memory (SRAM) cell includes a pair of cross-coupled inverters having a first node and a second node. A first transistor is coupled between the first node and a first bit line. A second transistor is coupled between the second node and a second bit line. A third transistor is coupled with the first node. The third transistor has a threshold voltage that is higher than that of a fourth transistor of the pair of cross-coupled inverters by about 10% or more. A fifth transistor is coupled between the third transistor and a third bit line

    摘要翻译： 静态随机存取存储器（SRAM）单元包括具有第一节点和第二节点的一对交叉耦合的反相器。 第一晶体管耦合在第一节点和第一位线之间。 第二晶体管耦合在第二节点和第二位线之间。 第三晶体管与第一节点耦合。 第三晶体管具有比该对交叉耦合的反相器对的第四晶体管的阈值电压高约10％以上的阈值电压。 第五晶体管耦合在第三晶体管和第三位线之间

    SRAM CELLS, MEMORY CIRCUITS, SYSTEMS, AND FABRICATION METHODS THEREOF
    4.
    发明申请
    SRAM CELLS, MEMORY CIRCUITS, SYSTEMS, AND FABRICATION METHODS THEREOF 有权
    SRAM电池，存储器电路，系统及其制造方法

    公开(公告)号：US20110063894A1

    公开(公告)日：2011-03-17

    申请号：US12877695

    申请日：2010-09-08

    申请人： Cheng Hung LEE ,  Hung-Jen LIAO

    发明人： Cheng Hung LEE ,  Hung-Jen LIAO

    IPC分类号： G11C11/00 ,  H01R43/00

    CPC分类号： G11C11/412

    摘要： A static random access memory (SRAM) cell includes a pair of cross-coupled inverters having a first node and a second node. A first transistor is coupled between the first node and a first bit line. A second transistor is coupled between the second node and a second bit line. A third transistor is coupled with the first node. The third transistor has a threshold voltage that is higher than that of a fourth transistor of the pair of cross-coupled inverters by about 10% or more. A fifth transistor is coupled between the third transistor and a third bit line

    摘要翻译： 静态随机存取存储器（SRAM）单元包括具有第一节点和第二节点的一对交叉耦合的反相器。 第一晶体管耦合在第一节点和第一位线之间。 第二晶体管耦合在第二节点和第二位线之间。 第三晶体管与第一节点耦合。 第三晶体管具有比该对交叉耦合的反相器对的第四晶体管的阈值电压高约10％以上的阈值电压。 第五晶体管耦合在第三晶体管和第三位线之间

    MEMORY EDGE CELL
    6.
    发明申请
    MEMORY EDGE CELL 有权
    记忆边缘细胞

    公开(公告)号：US20120206953A1

    公开(公告)日：2012-08-16

    申请号：US13025872

    申请日：2011-02-11

    申请人： Hong-Chen CHENG ,  Ming-Yi LEE ,  Kuo-Hua PAN ,  Jung-Hsuan CHEN ,  Li-Chun TIEN ,  Cheng Hung LEE ,  Hung-Jen LIAO

    发明人： Hong-Chen CHENG ,  Ming-Yi LEE ,  Kuo-Hua PAN ,  Jung-Hsuan CHEN ,  Li-Chun TIEN ,  Cheng Hung LEE ,  Hung-Jen LIAO

    IPC分类号： G11C5/06 ,  H01L25/00

    CPC分类号： G11C5/06 ,  G11C5/147 ,  G11C5/148 ,  G11C11/417

    摘要： A circuit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The PMOS transistors and the NMOS transistors are configured to provide a first voltage reference node having a first reference voltage and a second voltage reference node having a second reference voltage. The first reference voltage and the second reference voltage serve as a first reference voltage and a second reference voltage for a memory cell, respectively.

    摘要翻译： 电路包括第一PMOS晶体管，第二PMOS晶体管，第一NMOS晶体管，第二NMOS晶体管，第三NMOS晶体管和第四NMOS晶体管。 PMOS晶体管和NMOS晶体管被配置为提供具有第一参考电压的第一电压参考节点和具有第二参考电压的第二参考电压节点。 第一参考电压和第二参考电压分别用作存储器单元的第一参考电压和第二参考电压。

    MEMORY DEVICES
    7.
    发明申请
    MEMORY DEVICES 审中-公开
    内存设备

    公开(公告)号：US20120014158A1

    公开(公告)日：2012-01-19

    申请号：US12838572

    申请日：2010-07-19

    申请人： Ching-Wei WU ,  Cheng Hung LEE ,  Kuang Ting CHEN

    发明人： Ching-Wei WU ,  Cheng Hung LEE ,  Kuang Ting CHEN

    IPC分类号： G11C17/12

    CPC分类号： G11C17/12

    摘要： A memory device includes an array of transistors, a plurality of bit lines, and a plurality of source lines. The transistors include gate, drain and source terminals. The gate terminals are electrically coupled to word lines. The plurality of bit lines connect a power source to the drain terminals of the array of transistors and the plurality of source lines connect the power source to the source terminals of the array of transistors. The connections are made active during a standby mode, thereby limiting leakage current without entailing drawbacks associated with degraded memory access/cycle time.

    摘要翻译： 存储器件包括晶体管阵列，多个位线和多条源极线。 晶体管包括栅极，漏极和源极端子。 栅极端子电耦合到字线。 多个位线将电源连接到晶体管阵列的漏极端子，并且多个源极线将电源连接到晶体管阵列的源极端子。 在待机模式期间，这些连接被激活，从而限制泄漏电流，而不会引起与存储器访问/周期时间下降有关的缺点。

    MEMORY CHIP WITH MORE THAN ONE TYPE OF MEMORY CELL
    8.
    发明申请
    MEMORY CHIP WITH MORE THAN ONE TYPE OF MEMORY CELL 有权
    具有超过一种类型的记忆体的记忆芯片

    公开(公告)号：US20130010516A1

    公开(公告)日：2013-01-10

    申请号：US13178021

    申请日：2011-07-07

    申请人： Cheng Hung LEE ,  XiuLi YANG ,  Liangbo ZHUANG

    发明人： Cheng Hung LEE ,  XiuLi YANG ,  Liangbo ZHUANG

    IPC分类号： G11C5/06 ,  G06F17/50

    CPC分类号： G11C5/06 ,  G11C7/12 ,  G11C7/18 ,  G11C8/08 ,  G11C11/005

    摘要： A semiconductor memory chip that has word lines driven by respective word line drivers and bit lines to carry signals to respective bit line amplifiers/drivers with memory cells at intersections of the word lines and bit lines memory cells. The semiconductor memory chip including various memory cell types, the type of memory cell at an intersection based on a position of the intersection among the word lines and bit lines.

    摘要翻译： 一种半导体存储器芯片，其具有由相应的字线驱动器和位线驱动的字线，以将信号传送到具有位线和位线存储器单元的交叉处的存储器单元的各个位线放大器/驱动器。 包括各种存储单元类型的半导体存储器芯片，基于字线和位线之间的交点的位置的交叉路口处的存储单元的类型。

    MODIFIED DESIGN RULES TO IMPROVE DEVICE PERFORMANCE
    10.
    发明申请
    MODIFIED DESIGN RULES TO IMPROVE DEVICE PERFORMANCE 有权
    改进设计规范，以提高设备性能

    公开(公告)号：US20120061764A1

    公开(公告)日：2012-03-15

    申请号：US12879447

    申请日：2010-09-10

    申请人： Annie LUM ,  Derek C. TAO ,  Cheng Hung LEE ,  Chung-Ji LU ,  Hong-Chen CHENG ,  Vineet Kumar AGRAWAL ,  Keun-Young KIM ,  Pyong Yun CHO

    发明人： Annie LUM ,  Derek C. TAO ,  Cheng Hung LEE ,  Chung-Ji LU ,  Hong-Chen CHENG ,  Vineet Kumar AGRAWAL ,  Keun-Young KIM ,  Pyong Yun CHO

    IPC分类号： H01L27/088 ,  G06F17/50

    CPC分类号： G06F17/5068 ,  G06F17/5081 ,  G06F2217/12 ,  H01L27/0207 ,  H01L27/088 ,  Y02P90/265

    摘要： The layouts, device structures, and methods described above utilize dummy devices to extend the diffusion regions of edge structures and/or non-allowed structures to the dummy device. Such extension of diffusion regions resolves or reduces LOD and edge effect issues. In addition, treating the gate structure of a dummy device next to an edge device also allows only one dummy structure to be added next to the dummy device and saves the real estate on the semiconductor chip. The dummy devices are deactivated and their performance is not important. Therefore, utilizing dummy devices to extend the diffusion regions of edge structures and/or non-allowed structures according to design rules allows the resolution or reduction or LOD and edge effect issues without the penalty of yield reduction or increase in layout areas.

    摘要翻译： 上述布局，装置结构和方法利用虚设装置将边缘结构和/或非允许结构的扩散区域扩展到虚设装置。 这种扩散区域的扩展可解决或减少LOD和边缘效应问题。 此外，在边缘装置旁边处理伪装置的栅极结构也仅允许在虚设装置旁边添加一个虚拟结构，并将该不动产保存在半导体芯片上。 虚拟设备被禁用，其性能不重要。 因此，利用虚设装置根据设计规则扩展边缘结构和/或非允许结构的扩散区域允许分辨率或降低或LOD和边缘效应发生，而不会降低成品率或增加布局面积。