公开(公告)号：US07952911B2

公开(公告)日：2011-05-31

申请号：US12111905

申请日：2008-04-29

申请人： Cheng-Hung Lee ,  Ching-Wei Wu ,  Hung-Jen Liao

发明人： Cheng-Hung Lee ,  Ching-Wei Wu ,  Hung-Jen Liao

IPC分类号： G11C11/00

CPC分类号： G11C5/063 ,  G11C11/419

摘要： This invention discloses a static random access memory (SRAM) cell array structure which comprises a first and second bit-line coupled to a column of SRAM cells, the first and second bit-lines being substantially parallel to each other and formed by a first metal layer, and a first conductive line being placed between the first and second bit-lines and spanning across the column of SRAM cells without making conductive coupling thereto, the first conductive line being also formed by the first metal layer.

摘要翻译： 本发明公开了一种静态随机存取存储器（SRAM）单元阵列结构，其包括耦合到一列SRAM单元的第一和第二位线，第一和第二位线基本上彼此平行并由第一金属 层，并且第一导线被放置在第一和第二位线之间并跨越SRAM单元的列而不与其形成导电耦合，第一导电线也由第一金属层形成。

公开(公告)号：US20090268501A1

公开(公告)日：2009-10-29

申请号：US12111905

申请日：2008-04-29

申请人： Cheng-Hung Hung Lee ,  Ching-Wei Wu ,  Hung-Jen Liao

发明人： Cheng-Hung Hung Lee ,  Ching-Wei Wu ,  Hung-Jen Liao

IPC分类号： G11C5/06

CPC分类号： G11C5/063 ,  G11C11/419

摘要： This invention discloses a static random access memory (SRAM) cell array structure which comprises a first and second bit-line coupled to a column of SRAM cells, the first and second bit-lines being substantially parallel to each other and formed by a first metal layer, and a first conductive line being placed between the first and second bit-lines and spanning across the column of SRAM cells without making conductive coupling thereto, the first conductive line being also formed by the first metal layer.

摘要翻译： 本发明公开了一种静态随机存取存储器（SRAM）单元阵列结构，其包括耦合到一列SRAM单元的第一和第二位线，第一和第二位线基本上彼此平行并由第一金属 层，并且第一导线被放置在第一和第二位线之间并跨越SRAM单元的列而不与其形成导电耦合，第一导电线也由第一金属层形成。

公开(公告)号：US07502277B2

公开(公告)日：2009-03-10

申请号：US11599934

申请日：2006-11-15

申请人： Ching-Wei Wu ,  Cheng Hung Lee ,  Hung-Jen Liao

发明人： Ching-Wei Wu ,  Cheng Hung Lee ,  Hung-Jen Liao

IPC分类号： G11C8/00

CPC分类号： G11C11/412 ,  G11C8/08

摘要： This invention discloses an integrated circuit, which comprises a first and a second pull-down circuit controlled by a first and second signal, respectively, and coupled between a first node and a low voltage power supply (Vss), and a controllable pull-up circuit coupled between the first node and a complimentary high voltage power supply (Vcc), wherein when either the first or second signal is asserted to a predetermined logic state, the first node is pulled down to a logic LOW state.

摘要翻译： 本发明公开了一种集成电路，其包括分别由第一和第二信号控制并耦合在第一节点和低电压电源（Vss）之间的第一和第二下拉电路以及可控上拉 耦合在第一节点和互补高压电源（Vcc）之间的电路，其中当第一或第二信号被确定到预定逻辑状态时，第一节点被下拉到逻辑低电平状态。

公开(公告)号：US20080112213A1

公开(公告)日：2008-05-15

申请号：US11599934

申请日：2006-11-15

申请人： Ching-Wei Wu ,  Cheng Hung Lee ,  Hung-Jen Liao

发明人： Ching-Wei Wu ,  Cheng Hung Lee ,  Hung-Jen Liao

IPC分类号： G11C11/00 ,  G11C7/12 ,  G11C8/00

CPC分类号： G11C11/412 ,  G11C8/08

摘要： This invention discloses an integrated circuit, which comprises a first and a second pull-down circuit controlled by a first and second signal, respectively, and coupled between a first node and a low voltage power supply (Vss), and a controllable pull-up circuit coupled between the first node and a complimentary high voltage power supply (Vcc), wherein when either the first or second signal is asserted to a predetermined logic state, the first node is pulled down to a logic LOW state.

摘要翻译： 本发明公开了一种集成电路，其包括分别由第一和第二信号控制并耦合在第一节点和低电压电源（Vss）之间的第一和第二下拉电路以及可控上拉 耦合在第一节点和互补高压电源（Vcc）之间的电路，其中当第一或第二信号被确定到预定逻辑状态时，第一节点被下拉到逻辑低电平状态。

公开(公告)号：US08437210B2

公开(公告)日：2013-05-07

申请号：US13030722

申请日：2011-02-18

申请人： Ching-Wei Wu ,  Kuang Ting Chen ,  Cheng Hung Lee

发明人： Ching-Wei Wu ,  Kuang Ting Chen ,  Cheng Hung Lee

IPC分类号： G11C7/00

CPC分类号： G11C7/08 ,  G11C7/065

摘要： A circuit includes a first inverter including a first PMOS transistor and a first NMOS transistor, and a second inverter including a second PMOS transistor and a second NMOS transistor. A first node is connected to gates of the first PMOS transistor and the first NMOS transistor and drains of the second PMOS transistor and the second NMOS transistor. A second node is connected to gates of the second PMOS transistor and the second NMOS transistor and drains of the first PMOS transistor and the first NMOS transistor. The circuit further includes a first capacitor having a first capacitance connected to the first node; and a second capacitor having a second capacitance connected to the second node. The second capacitance is greater than the first capacitance.

摘要翻译： 电路包括：第一反相器，包括第一PMOS晶体管和第一NMOS晶体管;以及第二反相器，包括第二PMOS晶体管和第二NMOS晶体管。 第一节点连接到第一PMOS晶体管和第一NMOS晶体管的栅极以及第二PMOS晶体管和第二NMOS晶体管的漏极。 第二节点连接到第二PMOS晶体管和第二NMOS晶体管的栅极以及第一PMOS晶体管和第一NMOS晶体管的漏极。 电路还包括具有连接到第一节点的第一电容的第一电容器; 以及具有连接到第二节点的第二电容的第二电容器。 第二电容大于第一电容。

公开(公告)号：US20110242904A1

公开(公告)日：2011-10-06

申请号：US12983985

申请日：2011-01-04

申请人： Ching-Wei Wu ,  Cheng-Hung Lee ,  He-Zhou Wan ,  Wei-Yang Jiang

发明人： Ching-Wei Wu ,  Cheng-Hung Lee ,  He-Zhou Wan ,  Wei-Yang Jiang

IPC分类号： G11C16/08

CPC分类号： G11C8/08 ,  G11C17/14

摘要： A read only memory (ROM) and an operating method thereof are provided. The read only memory includes: a control circuit, powered by a first power source for outputting a control signal within a first voltage range; a voltage shifter, for expanding the amplitude of the control signal to a second voltage range; a word line driver, powered by a second power source with a voltage which is higher than that of the first power source, for driving one of a plurality of word lines of a read only memory cell array according to the control signal which is expanded to be within the second voltage range; and an input/output circuit, for connecting the plurality of bit lines to read out messages.

摘要翻译： 提供只读存储器（ROM）及其操作方法。 只读存储器包括：控制电路，由第一电源供电，用于在第一电压范围内输出控制信号; 电压移位器，用于将控制信号的振幅扩大到第二电压范围; 由具有比第一电源的电压高的第二电源供电的字线驱动器，用于根据扩展至的只读存储单元阵列的多个字线中的一个字线驱动 处于第二电压范围内; 以及用于连接多个位线以读出消息的输入/输出电路。

公开(公告)号：US20100259999A1

公开(公告)日：2010-10-14

申请号：US12754733

申请日：2010-04-06

申请人： Cheng Hung LEE ,  Ching-Wei WU ,  Bin SHENG ,  Hung-Jen LIAO

发明人： Cheng Hung LEE ,  Ching-Wei WU ,  Bin SHENG ,  Hung-Jen LIAO

IPC分类号： G11C7/00 ,  H03L5/00

CPC分类号： H01L27/1104 ,  G11C11/419

摘要： A keeper of an integrated circuit includes a first transistor having a first gate being coupled with an output end of an inverter. A second transistor is coupled with the first transistor in series. The second transistor has a second gate being coupled with an input end of the inverter.

摘要翻译： 集成电路的保持器包括具有与反相器的输出端耦合的第一栅极的第一晶体管。 第二晶体管与第一晶体管串联耦合。 第二晶体管具有与反相器的输入端耦合的第二栅极。

公开(公告)号：US20080229161A1

公开(公告)日：2008-09-18

申请号：US11686996

申请日：2007-03-16

申请人： Cheng-Hung Lee ,  Ching-Wei Wu ,  Chung-Cheng Chou ,  Hung-Jen Liao

发明人： Cheng-Hung Lee ,  Ching-Wei Wu ,  Chung-Cheng Chou ,  Hung-Jen Liao

IPC分类号： G11C29/00

CPC分类号： G11C29/50 ,  G11C29/70 ,  G11C29/80 ,  G11C2029/5004 ,  H01L22/22 ,  H01L27/1052

摘要： Memory products and manufacturing methods thereof. A memory product comprises at least one memory cell and at least one redundancy memory cell. The memory cell and the redundancy memory cell have different physical or electronic properties. The redundancy memory cells are used as repair schemes for the memory cell if the memory cell is determined to have experienced Vccmin failure.

摘要翻译： 内存产品及其制造方法。 存储器产品包括至少一个存储器单元和至少一个冗余存储单元。 存储单元和冗余存储单元具有不同的物理或电子特性。 如果确定存储器单元已经经历Vccmin故障，则冗余存储器单元被用作存储器单元的修复方案。

公开(公告)号：US06903436B1

公开(公告)日：2005-06-07

申请号：US10833968

申请日：2004-04-27

申请人： Ruei-Chin Luo ,  Chung-Cheng Chou ,  Ching-Wei Wu

发明人： Ruei-Chin Luo ,  Chung-Cheng Chou ,  Ching-Wei Wu

IPC分类号： G11C17/16 ,  G11C17/18 ,  H01L23/525 ,  H01L29/00 ,  H01L29/76

CPC分类号： G11C17/16 ,  G11C17/18 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： An improved a programmable electrical fuse device utilizing MOS oxide breakdown is described herein. The fuse device comprises a programmable MOS device having a first gate width, a reference MOS device having a second gate width that is substantially less than the first gate width, and a sense amplifier operable to detect a difference in current and generate a corresponding logical signal. According to one embodiment, the fuse device can be programmed only once to invert its logical state and thereby provide a changeable logical signal. This is done by applying an overvoltage signal to the programmable MOS device so that its oxide layer breaks down. Since the programmable MOS device and the reference MOS device are on opposite sides of the sense amplifier, an opposite logical signal is generated by shorting-out the programmable MOS device. According to another embodiment, the fuse device can be programmed and erased multiple times by breaking down oxide layers in MOS devices that are alternating sides of a sense amplifier.

摘要翻译： 本文描述了利用MOS氧化物击穿的改进的可编程电熔丝装置。 熔丝器件包括具有第一栅极宽度的可编程MOS器件，具有基本上小于第一栅极宽度的第二栅极宽度的参考MOS器件，以及用于检测电流差并产生相应逻辑信号的读出放大器 。 根据一个实施例，熔丝器件可以仅被编程一次以反转其逻辑状态，从而提供可变的逻辑信号。 这通过对可编程MOS器件施加过电压信号以使其氧化层发生故障来完成。 由于可编程MOS器件和参考MOS器件位于读出放大器的相对侧，所以通过短路可编程MOS器件产生相反的逻辑信号。 根据另一实施例，通过分解作为读出放大器的交替侧的MOS器件中的氧化物层，可以对熔丝器件进行多次编程和擦除。

公开(公告)号：US08565009B2

公开(公告)日：2013-10-22

申请号：US12767935

申请日：2010-04-27

申请人： Ching-Wei Wu ,  Lee Cheng Hung ,  Hung-Je Liao ,  Jui-Che Tsai

发明人： Ching-Wei Wu ,  Lee Cheng Hung ,  Hung-Je Liao ,  Jui-Che Tsai

IPC分类号： G11C11/00

CPC分类号： G11C8/08 ,  G11C8/16 ,  G11C11/413

摘要： Mechanisms for improving static noise margin and/or reducing misread current in multi-port devices are disclosed. In some embodiments related to dual port SRAM a suppress device (e.g., transistor) is provided at each word line port. When both ports are activated, both suppress devices are on and lower the voltage level of these ports, which in turn lower the voltage level at the node storing the data for the memory. As the voltage level at the data node is lowered, noise margin is improved and read disturb can be avoided.

摘要翻译： 公开了用于改善多端口设备中的静态噪声容限和/或减少误读电流的机构。 在与双端口SRAM相关的一些实施例中，在每个字线端口处提供抑制装置（例如，晶体管）。 当两个端口都被激活时，两个抑制装置都会接通和降低这些端口的电压电平，这又降低了存储存储器数据的节点处的电压电平。 随着数据节点处的电压电平降低，噪声容限得到改善，可以避免读取干扰。