公开(公告)号：US06903436B1

公开(公告)日：2005-06-07

申请号：US10833968

申请日：2004-04-27

申请人： Ruei-Chin Luo ,  Chung-Cheng Chou ,  Ching-Wei Wu

发明人： Ruei-Chin Luo ,  Chung-Cheng Chou ,  Ching-Wei Wu

IPC分类号： G11C17/16 ,  G11C17/18 ,  H01L23/525 ,  H01L29/00 ,  H01L29/76

CPC分类号： G11C17/16 ,  G11C17/18 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： An improved a programmable electrical fuse device utilizing MOS oxide breakdown is described herein. The fuse device comprises a programmable MOS device having a first gate width, a reference MOS device having a second gate width that is substantially less than the first gate width, and a sense amplifier operable to detect a difference in current and generate a corresponding logical signal. According to one embodiment, the fuse device can be programmed only once to invert its logical state and thereby provide a changeable logical signal. This is done by applying an overvoltage signal to the programmable MOS device so that its oxide layer breaks down. Since the programmable MOS device and the reference MOS device are on opposite sides of the sense amplifier, an opposite logical signal is generated by shorting-out the programmable MOS device. According to another embodiment, the fuse device can be programmed and erased multiple times by breaking down oxide layers in MOS devices that are alternating sides of a sense amplifier.

摘要翻译： 本文描述了利用MOS氧化物击穿的改进的可编程电熔丝装置。 熔丝器件包括具有第一栅极宽度的可编程MOS器件，具有基本上小于第一栅极宽度的第二栅极宽度的参考MOS器件，以及用于检测电流差并产生相应逻辑信号的读出放大器 。 根据一个实施例，熔丝器件可以仅被编程一次以反转其逻辑状态，从而提供可变的逻辑信号。 这通过对可编程MOS器件施加过电压信号以使其氧化层发生故障来完成。 由于可编程MOS器件和参考MOS器件位于读出放大器的相对侧，所以通过短路可编程MOS器件产生相反的逻辑信号。 根据另一实施例，通过分解作为读出放大器的交替侧的MOS器件中的氧化物层，可以对熔丝器件进行多次编程和擦除。

公开(公告)号：US20050149891A1

公开(公告)日：2005-07-07

申请号：US10752116

申请日：2004-01-06

申请人： Ruei-Chin Luo ,  Hung-Jen Liao

发明人： Ruei-Chin Luo ,  Hung-Jen Liao

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： The present invention relates to a method of creating a design for a semiconductor memory. In an embodiment, a memory compiler for a semiconductor memory has access to a set of leaf cell designs for use by the memory compiler, the leaf cell designs comprising a power management circuit design as a leaf cell for a memory circuit. A user may elect to allow enablement of an ultra low power feature and the memory compiler creates a design which incorporates the power management circuit in a compiled semiconductor memory macro when the user-selectable option is enabled. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

摘要翻译： 本发明涉及一种创建半导体存储器的设计的方法。 在一个实施例中，用于半导体存储器的存储器编译器可以访问由存储器编译器使用的一组叶单元设计，叶单元设计包括作为存储器电路的叶单元的功率管理电路设计。 用户可以选择允许启用超低功率特征，并且当用户可选择的选项被启用时，存储器编译器创建将编译半导体存储器宏中的电源管理电路合并的设计。 要强调的是，该摘要被提供以符合要求摘要的规则，这将允许搜索者或其他读者快速确定技术公开的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

公开(公告)号：US07137079B2

公开(公告)日：2006-11-14

申请号：US10752116

申请日：2004-01-06

申请人： Ruei-Chin Luo ,  Hung-Jen Liao

发明人： Ruei-Chin Luo ,  Hung-Jen Liao

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： The present invention relates to a method of creating a design for a semiconductor memory. In an embodiment, a memory compiler for a semiconductor memory has access to a set of leaf cell designs for use by the memory compiler, the leaf cell designs comprising a power management circuit design as a leaf cell for a memory circuit. A user may elect to allow enablement of an ultra low power feature and the memory compiler creates a design which incorporates the power management circuit in a compiled semiconductor memory macro when the user-selectable option is enabled.

摘要翻译： 本发明涉及一种创建半导体存储器的设计的方法。 在一个实施例中，用于半导体存储器的存储器编译器可以访问由存储器编译器使用的一组叶单元设计，叶单元设计包括作为存储器电路的叶单元的功率管理电路设计。 用户可以选择允许启用超低功耗特征，并且当用户可选择选项被启用时，存储器编译器创建将编译半导体存储器宏中的电源管理电路合并的设计。