公开(公告)号：US20090268501A1

公开(公告)日：2009-10-29

申请号：US12111905

申请日：2008-04-29

申请人： Cheng-Hung Hung Lee ,  Ching-Wei Wu ,  Hung-Jen Liao

发明人： Cheng-Hung Hung Lee ,  Ching-Wei Wu ,  Hung-Jen Liao

IPC分类号： G11C5/06

CPC分类号： G11C5/063 ,  G11C11/419

摘要： This invention discloses a static random access memory (SRAM) cell array structure which comprises a first and second bit-line coupled to a column of SRAM cells, the first and second bit-lines being substantially parallel to each other and formed by a first metal layer, and a first conductive line being placed between the first and second bit-lines and spanning across the column of SRAM cells without making conductive coupling thereto, the first conductive line being also formed by the first metal layer.

摘要翻译： 本发明公开了一种静态随机存取存储器（SRAM）单元阵列结构，其包括耦合到一列SRAM单元的第一和第二位线，第一和第二位线基本上彼此平行并由第一金属 层，并且第一导线被放置在第一和第二位线之间并跨越SRAM单元的列而不与其形成导电耦合，第一导电线也由第一金属层形成。

公开(公告)号：US07190626B2

公开(公告)日：2007-03-13

申请号：US11128846

申请日：2005-05-13

申请人： Cheng-Hung Lee ,  Ching-Wei Wu ,  Hung-Jen Liao

发明人： Cheng-Hung Lee ,  Ching-Wei Wu ,  Hung-Jen Liao

IPC分类号： G11C7/00

CPC分类号： G11C17/12 ,  G11C7/12 ,  G11C17/18

摘要： A memory access method and a memory system are disclosed for shortening a memory cell access time. The memory system comprises one or more memory cells, at least one bit-line discharge subsystem having one or more discharge modules, each discharge module coupled to a bit-line connecting to one or more memory cells for discharging a voltage level of the bit-line upon a triggering of a discharge control signal, at least one sense amplifier coupled to the bit-line for determining data stored in a selected memory cell, at least one latch module for storing the determined data from the sense amplifier upon a triggering of a latch enable signal, wherein the discharge control signal is triggered prior to the triggering of the latch enable signal so that the voltage level of the bit-line is discharged for allowing an accelerated reading of the data.

摘要翻译： 公开了一种用于缩短存储器单元访问时间的存储器存取方法和存储器系统。 存储器系统包括一个或多个存储器单元，至少一个位线放电子系统，具有一个或多个放电模块，每个放电模块耦合到连接到一个或多个存储器单元的位线， 在触发放电控制信号时，连接到位线的至少一个读出放大器用于确定存储在所选择的存储器单元中的数据，至少一个锁存模块，用于在触发放大控制信号时从读出放大器存储所确定的数据 锁存使能信号，其中在触发锁存器使能信号之前触发放电控制信号，使得位线的电压电平被放电以允许数据的加速读取。

公开(公告)号：US08488395B2

公开(公告)日：2013-07-16

申请号：US12754733

申请日：2010-04-06

申请人： Cheng Hung Lee ,  Ching-Wei Wu ,  Bin Sheng ,  Hung-Jen Liao

发明人： Cheng Hung Lee ,  Ching-Wei Wu ,  Bin Sheng ,  Hung-Jen Liao

IPC分类号： G11C7/00

CPC分类号： H01L27/1104 ,  G11C11/419

摘要： A keeper of an integrated circuit includes a first transistor having a first gate being coupled with an output end of an inverter. A second transistor is coupled with the first transistor in series. The second transistor has a second gate being coupled with an input end of the inverter.

摘要翻译： 集成电路的保持器包括具有与反相器的输出端耦合的第一栅极的第一晶体管。 第二晶体管与第一晶体管串联耦合。 第二晶体管具有与反相器的输入端耦合的第二栅极。

公开(公告)号：US08395950B2

公开(公告)日：2013-03-12

申请号：US12968582

申请日：2010-12-15

申请人： Tzu-Kuei Lin ,  Hung-Jen Liao ,  Shao-Yu Chou ,  Ching-Wei Wu

发明人： Tzu-Kuei Lin ,  Hung-Jen Liao ,  Shao-Yu Chou ,  Ching-Wei Wu

IPC分类号： G11C7/00

CPC分类号： G11C7/222

摘要： A memory device is provided with memory components and a clock skew generator, supporting at least two read and write operations that can occur coincidentally in read-read, read-write and write-write modes of operation of the memory device. The clock skew generator produces at least two stable and balanced clock channels carrying the at least two clock signals and varies relative timing of the clock signal edges so as to displace the edges in time, in those modes of operation wherein simultaneous edges would lead to detrimental loading.

摘要翻译： 存储器件具有存储器组件和时钟偏斜发生器，支持在存储器件的读取，读写和写入 - 写入操作模式中可能巧合地发生的至少两个读和写操作。 时钟偏移发生器产生至少两个稳定和平衡的时钟通道，其承载至少两个时钟信号，并且改变时钟信号边沿的相对定时，从而在这些操作模式中随时移动边缘，其中同时的边缘将导致有害的 加载。

公开(公告)号：US20090109768A1

公开(公告)日：2009-04-30

申请号：US11924437

申请日：2007-10-25

申请人： Cheng-Hung Lee ,  Ping-Wei Wang ,  Ching-Wei Wu ,  Shu-Hsuan Lin ,  Feng-Ming Chang ,  Hung-Jen Liao

发明人： Cheng-Hung Lee ,  Ping-Wei Wang ,  Ching-Wei Wu ,  Shu-Hsuan Lin ,  Feng-Ming Chang ,  Hung-Jen Liao

IPC分类号： G11C7/00

CPC分类号： G11C11/412 ,  H01L27/1104

摘要： An SRAM device includes: a first group of memory cells connected to a first local bit line and a first local complementary bit line for accessing data nodes thereof; a second group of memory cells connected to a second local bit line and a second local complementary bit line for accessing data nodes thereof; and a global bit line and a global complementary bit line connected to the first and second local bit lines for accessing data nodes of the first and second groups of memory cells, wherein the first local bit line, the first local complementary bit line, the second local bit line, the second local complementary bit line, the global bit line and the global complementary bit line are constructed on a same metallization level in the SRAM device.

摘要翻译： SRAM器件包括：连接到第一本地位线的第一组存储器单元和用于访问其数据节点的第一局部互补位线; 连接到第二本地位线的第二组存储器单元和用于访问其数据节点的第二局部互补位线; 以及连接到第一和第二本地位线的全局位线和全局互补位线，用于访问第一和第二组存储器单元的数据节点，其中第一局部位线，第一局部互补位线，第二局部位线 局部位线，第二局部互补位线，全局位线和全局互补位线构成在SRAM器件中相同的金属化电平上。

公开(公告)号：US20060256635A1

公开(公告)日：2006-11-16

申请号：US11128846

申请日：2005-05-13

申请人： Cheng-Hung Lee ,  Ching-Wei Wu ,  Hung-Jen Liao

发明人： Cheng-Hung Lee ,  Ching-Wei Wu ,  Hung-Jen Liao

IPC分类号： G11C7/00

CPC分类号： G11C17/12 ,  G11C7/12 ,  G11C17/18

摘要： A memory access method and a memory system are disclosed for shortening a memory cell access time. The memory system comprises one or more memory cells, at least one bit-line discharge subsystem having one or more discharge modules, each discharge module coupled to a bit-line connecting to one or more memory cells for discharging a voltage level of the bit-line upon a triggering of a discharge control signal, at least one sense amplifier coupled to the bit-line for determining data stored in a selected memory cell, at least one latch module for storing the determined data from the sense amplifier upon a triggering of a latch enable signal, wherein the discharge control signal is triggered prior to the triggering of the latch enable signal so that the voltage level of the bit-line is discharged for allowing an accelerated reading of the data.

摘要翻译： 公开了一种用于缩短存储器单元访问时间的存储器存取方法和存储器系统。 存储器系统包括一个或多个存储器单元，至少一个位线放电子系统，具有一个或多个放电模块，每个放电模块耦合到连接到一个或多个存储器单元的位线， 在触发放电控制信号时，连接到位线的至少一个读出放大器用于确定存储在所选择的存储器单元中的数据，至少一个锁存模块，用于在触发放大控制信号时从读出放大器存储所确定的数据 锁存使能信号，其中在触发锁存器使能信号之前触发放电控制信号，使得位线的电压电平被放电以允许数据的加速读取。

公开(公告)号：US07613054B2

公开(公告)日：2009-11-03

申请号：US11924437

申请日：2007-10-25

申请人： Cheng-Hung Lee ,  Ping-Wei Wang ,  Ching-Wei Wu ,  Shu-Hsuan Lin ,  Feng-Ming Chang ,  Hung-Jen Liao

发明人： Cheng-Hung Lee ,  Ping-Wei Wang ,  Ching-Wei Wu ,  Shu-Hsuan Lin ,  Feng-Ming Chang ,  Hung-Jen Liao

IPC分类号： G11C7/00

CPC分类号： G11C11/412 ,  H01L27/1104

摘要： An SRAM device includes: a first group of memory cells connected to a first local bit line and a first local complementary bit line for accessing data nodes thereof; a second group of memory cells connected to a second local bit line and a second local complementary bit line for accessing data nodes thereof; and a global bit line and a global complementary bit line connected to the first and second local bit lines for accessing data nodes of the first and second groups of memory cells, wherein the first local bit line, the first local complementary bit line, the second local bit line, the second local complementary bit line, the global bit line and the global complementary bit line are constructed on a same metallization level in the SRAM device.

摘要翻译： SRAM器件包括：连接到第一本地位线的第一组存储器单元和用于访问其数据节点的第一局部互补位线; 连接到第二本地位线的第二组存储器单元和用于访问其数据节点的第二局部互补位线; 以及连接到第一和第二本地位线的全局位线和全局互补位线，用于访问第一和第二组存储器单元的数据节点，其中第一局部位线，第一局部互补位线，第二局部位线 局部位线，第二局部互补位线，全局位线和全局互补位线构成在SRAM器件中相同的金属化电平上。

公开(公告)号：US20080229161A1

公开(公告)日：2008-09-18

申请号：US11686996

申请日：2007-03-16

申请人： Cheng-Hung Lee ,  Ching-Wei Wu ,  Chung-Cheng Chou ,  Hung-Jen Liao

发明人： Cheng-Hung Lee ,  Ching-Wei Wu ,  Chung-Cheng Chou ,  Hung-Jen Liao

IPC分类号： G11C29/00

CPC分类号： G11C29/50 ,  G11C29/70 ,  G11C29/80 ,  G11C2029/5004 ,  H01L22/22 ,  H01L27/1052

摘要： Memory products and manufacturing methods thereof. A memory product comprises at least one memory cell and at least one redundancy memory cell. The memory cell and the redundancy memory cell have different physical or electronic properties. The redundancy memory cells are used as repair schemes for the memory cell if the memory cell is determined to have experienced Vccmin failure.

摘要翻译： 内存产品及其制造方法。 存储器产品包括至少一个存储器单元和至少一个冗余存储单元。 存储单元和冗余存储单元具有不同的物理或电子特性。 如果确定存储器单元已经经历Vccmin故障，则冗余存储器单元被用作存储器单元的修复方案。

公开(公告)号：US07952911B2

公开(公告)日：2011-05-31

申请号：US12111905

申请日：2008-04-29

申请人： Cheng-Hung Lee ,  Ching-Wei Wu ,  Hung-Jen Liao

发明人： Cheng-Hung Lee ,  Ching-Wei Wu ,  Hung-Jen Liao

IPC分类号： G11C11/00

CPC分类号： G11C5/063 ,  G11C11/419

摘要： This invention discloses a static random access memory (SRAM) cell array structure which comprises a first and second bit-line coupled to a column of SRAM cells, the first and second bit-lines being substantially parallel to each other and formed by a first metal layer, and a first conductive line being placed between the first and second bit-lines and spanning across the column of SRAM cells without making conductive coupling thereto, the first conductive line being also formed by the first metal layer.

摘要翻译： 本发明公开了一种静态随机存取存储器（SRAM）单元阵列结构，其包括耦合到一列SRAM单元的第一和第二位线，第一和第二位线基本上彼此平行并由第一金属 层，并且第一导线被放置在第一和第二位线之间并跨越SRAM单元的列而不与其形成导电耦合，第一导电线也由第一金属层形成。

公开(公告)号：US07502277B2

公开(公告)日：2009-03-10

申请号：US11599934

申请日：2006-11-15

申请人： Ching-Wei Wu ,  Cheng Hung Lee ,  Hung-Jen Liao

发明人： Ching-Wei Wu ,  Cheng Hung Lee ,  Hung-Jen Liao

IPC分类号： G11C8/00

CPC分类号： G11C11/412 ,  G11C8/08

摘要： This invention discloses an integrated circuit, which comprises a first and a second pull-down circuit controlled by a first and second signal, respectively, and coupled between a first node and a low voltage power supply (Vss), and a controllable pull-up circuit coupled between the first node and a complimentary high voltage power supply (Vcc), wherein when either the first or second signal is asserted to a predetermined logic state, the first node is pulled down to a logic LOW state.

摘要翻译： 本发明公开了一种集成电路，其包括分别由第一和第二信号控制并耦合在第一节点和低电压电源（Vss）之间的第一和第二下拉电路以及可控上拉 耦合在第一节点和互补高压电源（Vcc）之间的电路，其中当第一或第二信号被确定到预定逻辑状态时，第一节点被下拉到逻辑低电平状态。