公开(公告)号：US5903230A

公开(公告)日：1999-05-11

申请号：US899205

申请日：1997-07-23

申请人： Charles J. Masenas

发明人： Charles J. Masenas

IPC分类号： H03M7/40 ,  G06T9/00 ,  H03M7/30 ,  H03M7/00

CPC分类号： G06T9/005 ,  H03M7/3086

摘要： A data processing system having a compression and decompression apparatus based on the Lempel-Ziv algorithm. The compression apparatus includes an array section having a circular history CAM unit for receiving and storing one or more data elements and a coding unit for determining whether received data elements previously have been stored in the history CAM unit and are a candidate for compression. If a received data element matches at least one of the stored data elements, a PS logic section determines whether there is the presence of a string. An encoding section identifies the address of the matching stored data element in a string and the length of the string. The compression apparatus generates a compression token comprising an identification of whether a data element is compressed, the length of the coded data within a plurality of predetermined data length categories and an address. The compression apparatus uses a particular hardware implementation of the PS logic section.

摘要翻译： 一种具有基于Lempel-Ziv算法的压缩和解压缩装置的数据处理系统。 压缩装置包括具有圆形历史CAM单元的阵列部分，用于接收和存储一个或多个数据元素，以及编码单元，用于确定接收的数据元素是否已经存储在历史CAM单元中，并且是用于压缩的候选。 如果接收的数据元素与所存储的数据元素中的至少一个匹配，则PS逻辑部分确定是否存在字符串。 编码部分标识字符串中匹配的存储数据元素的地址和字符串的长度。 压缩装置生成压缩令牌，其包括数据元素是否被压缩的标识，多个预定数据长度类别内的编码数据的长度以及地址。 压缩装置使用PS逻辑部分的特定硬件实现。

公开(公告)号：US07088190B2

公开(公告)日：2006-08-08

申请号：US10709811

申请日：2004-05-28

申请人： John S. Austin ,  Melissa A. Beacom ,  Charles J. Masenas

发明人： John S. Austin ,  Melissa A. Beacom ,  Charles J. Masenas

IPC分类号： H03B5/24

CPC分类号： H03K3/012 ,  H03K3/0315

摘要： A voltage-controlled oscillator (VCO) comprising an odd number of delay stage circuits. Each delay stage circuit operates between supply voltages VDD and VSS (VDD>VSS) and comprises (1) an input node, (2) an output node, (3) an inverting circuit, and (4) an electric discharge path coupling the output node to VSS. The electric discharge path includes a switch circuit and a resistance adjusting circuit electrically coupled in series between the output node and VSS. In response to an input signal rising at the input node, the inverting circuit decreases an output signal at the output node, and the electric discharge path opens to help pull the output signal down faster. In response to an input signal falling at the input node, the inverting circuit increases the output signal at the output node, and the electric discharge path closes to minimize its own effect.

摘要翻译： 包括奇数个延迟级电路的压控振荡器（VCO）。 每个延迟级电路在电源电压VDD和VSS（VDD> VSS）之间工作，并且包括（1）输入节点，（2）输出节点，（3）反相电路，以及（4）将输出 节点到VSS。 放电路径包括在输出节点和VSS之间串联电耦合的开关电路和电阻调节电路。 响应于在输入节点处上升的输入信号，反相电路减小输出节点处的输出信号，并且放电路径打开以帮助较快地拉出输出信号。 响应于在输入节点处的输入信号，反相电路增加输出节点处的输出信号，并且放电路径关闭以最小化其自身的效果。

公开(公告)号：US06603416B2

公开(公告)日：2003-08-05

申请号：US09968218

申请日：2001-10-01

申请人： Charles J. Masenas ,  Chad E. Mitchell ,  Steven J. Tanghe ,  Sharon L. Von Bruns

发明人： Charles J. Masenas ,  Chad E. Mitchell ,  Steven J. Tanghe ,  Sharon L. Von Bruns

IPC分类号： H03M112

CPC分类号： H03M1/1033 ,  H03M1/36

摘要： A method and structure for calibrating an analog to digital converter comprises an input signal; a driver receiving the input signal, wherein the driver outputs a driver output signal; a flash circuit receiving the driver output signal, wherein the flash circuit outputs a comparison result equaling 2n−1 digital outputs; an encoding logic unit encoding the comparison result into n digital bits as an output signal; a calibration engine outputting a calibration input adjust signal, a reference adjust signal, a driver gain adjust signal, a driver offset adjust signal; and a calibration input circuit receiving the calibration input adjust signal, wherein the driver receives the driver gain adjust signal and the driver offset adjust signal, wherein the flash circuit receives the reference adjust signal, wherein the calibration engine receives n digital bits, and controls an operation of the driver or flash circuit based on the output signal.

摘要翻译： 用于校准模数转换器的方法和结构包括输入信号; 接收所述输入信号的驱动器，其中所述驱动器输出驱动器输出信号; 接收驱动器输出信号的闪光电路，其中闪光电路输出等于2n-1个数字输出的比较结果; 编码逻辑单元，将比较结果编码为n个数字位作为输出信号; 输出校准输入调整信号的校准引擎，基准调整信号，驾驶员增益调整信号，驾驶员偏移调整信号; 以及校准输入电路，其接收所述校准输入调整信号，其中所述驾驶员接收所述驾驶员增益调整信号和所述驾驶员偏移调整信号，其中所述闪光电路接收所述参考调整信号，其中所述校准引擎接收n个数字位， 基于输出信号对驱动器或闪存电路进行操作。

公开(公告)号：US6011423A

公开(公告)日：2000-01-04

申请号：US862896

申请日：1997-05-23

申请人： Arnold E. Baizley ,  Anthony R. Bonaccio ,  Charles J. Masenas ,  Steven J. Tanghe

发明人： Arnold E. Baizley ,  Anthony R. Bonaccio ,  Charles J. Masenas ,  Steven J. Tanghe

IPC分类号： H03K17/0416 ,  H03K19/013 ,  H03K17/56

CPC分类号： H03K19/013 ,  H03K17/04166

摘要： A voltage boosting circuit for an "H-driver," providing for each "pull-up" switch in the H-driver a switching shunt that charges a capacitor from a supply voltage when the "pull-up" switch is open and couples the capacitor directly to the write head when the "pull-up" switch is closed. The side of the capacitor which is not directly coupled to the write head is coupled to the data signal (or its inverse, in the case of the capacitor for the otherwise identical circuit serving the parallel half of the "H-driver") through a buffer which sets the voltage at the signal level (or its inverse), thereby dumping the charge to the write head and elevating the voltage of the write head significantly above the supply voltage. The identical circuit serving the parallel half of the "H-driver" similarly boosts the negative going transition voltage.

摘要翻译： 用于“H驱动器”的升压电路为H驱动器中的每个“上拉”开关提供一个开关分流器，当“上拉”开关断开时，电源从电源电压充电，并将 当“上拉”开关闭合时，电容器直接连接到写入头。 不直接耦合到写头的电容器的一侧耦合到数据信号（或者在与“H驱动器”的平行半部分相同的电路的电容器的情况下，其反相）通过 缓冲器将电压设置在信号电平（或其反相），从而将电荷转移到写入头，并将写入头的电压显着地高于电源电压。 用于“H驱动器”的并行半部分的相同电路同样提高了负向转变电压。

公开(公告)号：US5771010A

公开(公告)日：1998-06-23

申请号：US408577

申请日：1995-03-22

申请人： Charles J. Masenas

发明人： Charles J. Masenas

IPC分类号： H03M7/40 ,  G06T9/00 ,  H03M7/30

CPC分类号： G06T9/005 ,  H03M7/3086

摘要： A data processing system having a compression and decompression apparatus based on the Lempel-Ziv algorithm. The compression apparatus includes an array section having a circular history CAM unit for receiving and storing one or more data elements and a coding unit for determining whether received data elements previously have been stored in the history CAM unit and are a candidate for compression. If a received data element matches at least one of the stored data elements, a PS logic section determines whether there is the presence of a string. An encoding section identifies the address of the matching stored data element in a string and the length of the string. The compression apparatus generates a compression token comprising an identification of whether a data element is compressed, the length of the coded data within a plurality of predetermined data length categories and an address. The compression apparatus uses a particular hardware implementation of the PS logic section.

公开(公告)号：US5629650A

公开(公告)日：1997-05-13

申请号：US593755

申请日：1996-01-29

申请人： John E. Gersbach ,  Masayuki Hayashi ,  Charles J. Masenas

发明人： John E. Gersbach ,  Masayuki Hayashi ,  Charles J. Masenas

IPC分类号： H03L7/089 ,  H03L7/099 ,  H03L7/085

CPC分类号： H03L7/0891 ,  H03L7/099 ,  H03L2207/06

摘要： According to the preferred embodiment, a self-biased phase-locked loop is provided that overcomes the limitations of the prior art bias methods and apparatus. In general, a self-biased current controlled semiconductor device, typically a current controlled oscillator, is self biased by the use of a first feedback path, typically provided by a phase-locked loop, where the feedback path provides a control current for controlling the current controlled device. A second feedback path, typically a pair current mirrors, serves as a bias loop having unity gain. The bias loop provides a bias current that is responsive to the control current. This device has the advantage of being self biasing, thus no other biasing circuitry is required.

摘要翻译： 根据优选实施例，提供克服现有技术偏压方法和装置的限制的自偏置锁相环。 通常，自偏置电流控制半导体器件（通常为电流控制振荡器）通过使用通常由锁相环路提供的第一反馈路径自偏置，其中反馈路径提供控制电流以控制 电流控制装置 第二反馈路径（通常为一对电流镜）用作具有单位增益的偏置环路。 偏置环路提供响应于控制电流的偏置电流。 该器件具有自偏置的优点，因此不需要其它偏置电路。

公开(公告)号：US07248838B2

公开(公告)日：2007-07-24

申请号：US11410829

申请日：2006-04-24

申请人： Kenneth J. Goodnow ,  Riyon W. Harding ,  Charles J. Masenas ,  Jason M. Norman ,  Sebastian T. Ventrone

发明人： Kenneth J. Goodnow ,  Riyon W. Harding ,  Charles J. Masenas ,  Jason M. Norman ,  Sebastian T. Ventrone

IPC分类号： H04B1/00 ,  H04B7/00

CPC分类号： H04B1/38

摘要： A communication system for transmitting data between cores embedded in an integrated circuit on a silicon chip. Communication system includes transmitter circuitry for wirelessly transmitting data between cores and receiver circuitry for wirelessly receiving the transmission of data from other cores. Both transmitter circuitry and receiver circuitry may include of a phase-locked loop circuit having a voltage-controlled oscillator. Each core may transmit and receive data on a unique frequency with respect to other cores embedded in an integrated circuit on a silicon chip or transmit and receive data on the same frequency as other cores embedded in an integrated circuit on a silicon chip. Groups of cores may share transmitter and receiver circuitry.

摘要翻译： 一种用于在嵌入在硅芯片上的集成电路中的核之间传输数据的通信系统。 通信系统包括用于在核心和接收机电路之间无线地传输数据的发射机电路，用于无线地接收来自其他核的数据传输。 发射机电路和接收机电路都可以包括具有压控振荡器的锁相环电路。 每个核心可以相对于嵌入在硅芯片上的集成电路中的其它核心以独特的频率发送和接收数据，或者以与嵌入在硅芯片上的集成电路中的其它芯片相同的频率发送和接收数据。 核心组可以共享发射机和接收机电路。

公开(公告)号：US06954088B2

公开(公告)日：2005-10-11

申请号：US10707177

申请日：2003-11-25

申请人： Charles J. Masenas

发明人： Charles J. Masenas

IPC分类号： H03B5/12 ,  H03C3/00 ,  H03L7/099

CPC分类号： H03L7/099 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243

摘要： A structure and associated method for controlling an amplitude of oscillation in a voltage controlled oscillator. The voltage controlled oscillator circuit comprises a drive circuit, an inductor/capacitor (LC) tank circuit, and a diode. The LC tank circuit and the drive circuit collectively comprise a first oscillating node and a second oscillating node. The first oscillating node is adapted to have a first voltage. The second oscillating node is adapted to have a second voltage. The first diode is adapted to control an amplitude of the first voltage and an amplitude of the second voltage.

摘要翻译： 用于控制压控振荡器中的振荡幅度的结构和相关方法。 压控振荡器电路包括驱动电路，电感器/电容器（LC）电路和二极管。 LC槽电路和驱动电路共同包括第一振荡节点和第二振荡节点。 第一振荡节点适于具有第一电压。 第二振荡节点适于具有第二电压。 第一二极管适于控制第一电压的幅度和第二电压的幅度。

公开(公告)号：US06563388B2

公开(公告)日：2003-05-13

申请号：US09833192

申请日：2001-04-11

申请人： Charles J. Masenas ,  Troy A. Seman

发明人： Charles J. Masenas ,  Troy A. Seman

IPC分类号： H03L700

CPC分类号： H03L7/093 ,  H03L7/0893 ,  H03L7/18 ,  H03L2207/04

摘要： A complementary metal oxide semiconductor PLL includes an input for receiving a reference frequency and a feedback loop for determining a phase error based on the reference frequency. The feedback loop includes a calibration DAC (amplifier with a digital gain control input) and a bandwidth DAC in series. The ICO controller is well known in control theory as a PI or proportional-integral controller. A proportional path supplies a proportional signal to the calibration amplifier and an integral path supplies an integral signal (a signal that is integrated in time) to the calibration amplifier.

公开(公告)号：US06525615B1

公开(公告)日：2003-02-25

申请号：US09617259

申请日：2000-07-14

申请人： Charles J. Masenas ,  Troy A. Seman

发明人： Charles J. Masenas ,  Troy A. Seman

IPC分类号： H03L708

CPC分类号： G11B20/1025 ,  G11B5/5569 ,  G11B20/1403 ,  G11B21/18 ,  H03L7/087 ,  H03L7/091 ,  H03L7/0996 ,  H03L7/0998 ,  H03L7/18

摘要： The present invention provides an improved method and apparatus for independently controlling phase and frequency using an oscillator having a plurality of stages in combination with a phase selector within a digitally controlled phase-locked loop, preferably, a read phase locked loop. The present invention provides a digitally controlled variable phase of the read timing loop in read channel integrated circuits associated with data storage devices. The phase selector has a digitally controlled fine interpolator with 12 states for further fine interpolation between at least two multiplexer phase outputs to provide a single phase output selected from a range comprising at least 2&pgr; in selectable variable phase increments of 2&pgr;/96 radian. The combined oscillator with the phase selector within a phase locked loop controls phase by exact fractional increments of equally space phases of the operating frequency within the phase locked loop, therein controlling phase at all operating frequencies.

摘要翻译： 本发明提供一种用于使用具有多个级的振荡器来独立地控制相位和频率的改进的方法和装置，该振荡器与数字控制锁相环内的相位选择器组合，优选地是读锁相环。 本发明提供了与数据存储装置相关联的读通道集成电路中的读定时环的数字控制可变相位。 相位选择器具有数字控制的精细内插器，其具有12个状态用于在至少两个多路复用器相位输出之间进一步精细内插，以提供从包含至少2pi的范围中选择的单相输出，所述范围包括2pi / 96弧度的可选可变相位增量。 具有锁相环内的相位选择器的组合振荡器通过在锁相环内工作频率的相等空间相位的精确分数增量控制相位，其中控制所有工作频率的相位。