公开(公告)号：US08302037B2

公开(公告)日：2012-10-30

申请号：US12494642

申请日：2009-06-30

Applicant: Igor Arsovski ,  Anthony R Bonaccio ,  Hayden (Clay) Cranford, Jr. ,  Joseph A Iadanza ,  Pradeep Thiagarajan ,  Sebastian T Ventrone ,  Benjamin T Voegeli

Inventor： Igor Arsovski ,  Anthony R Bonaccio ,  Hayden (Clay) Cranford, Jr. ,  Joseph A Iadanza ,  Pradeep Thiagarajan ,  Sebastian T Ventrone ,  Benjamin T Voegeli

IPC: G06F17/50

CPC classification number: H03K19/09432 ,  H03K19/018528

Abstract: A differential system producing differential signals with offset cancellation utilizing a double differential input pair system is disclosed. It uses two parallel differential transistor pairs which are intentionally skewed. Nominally, the differential pairs are skewed in opposite direction from each, but with equal magnitude, so that the combination of the two differential pairs is nominally balanced. The current through each differential pair is then increased or decreased until any offset is sufficiently cancelled, using a selection means for providing an equi-potential value to first and second differential inputs in a calibration mode of the system and a comparison means for comparing first and second differential outputs in a calibration mode to determine the offset of the system.

Abstract translation: 公开了一种使用双差分输入对系统产生具有偏移消除的差分信号的差分系统。 它使用两个有意偏斜的并联差分晶体管对。 名义上，差分对在每个方向相反的方向上倾斜，但是具有相等的幅度，使得两个差分对的组合被名义上平衡。 然后，使用用于在系统的校准模式中为第一和第二差分输入提供等电位值的选择装置，增加或减少通过每个差分对的电流，直到任何偏移被充分抵消为止，以及用于比较第一和第 第二差分输出在校准模式下确定系统的偏移。

公开(公告)号：US20120168416A1

公开(公告)日：2012-07-05

申请号：US12984638

申请日：2011-01-05

Applicant: Richard S. Graf ,  Keishi Okamoto ,  Faraydon Pakbaz ,  Jack R. Smith ,  Sebastian T. Ventrone

Inventor： Richard S. Graf ,  Keishi Okamoto ,  Faraydon Pakbaz ,  Jack R. Smith ,  Sebastian T. Ventrone

IPC: H05B3/00 ,  G06F17/50

CPC classification number: H05B1/0227 ,  G05D23/1934

Abstract: Disclosed are embodiments of an integrated circuit chip designed for reliability at low ambient temperatures. The chip substrate can be divided into zones, including at least one temperature-sensitive zone (TSZ) that contains one or more temperature-sensitive circuits. Temperature sensor(s) can be positioned in the semiconductor substrate adjacent to the TSZ. Thermal radiator(s) can be embedded in a metal wiring layer and aligned above the TSZ. The temperature sensor(s) can be operatively connected to the thermal radiator(s) and can trigger operation of the thermal radiator(s) when the temperature in the TSZ is below a predetermined threshold temperature. Additionally, an on-chip power control system can be operatively connected to the thermal radiator(s) so that operation of the thermal radiator(s) is only triggered when a circuit within the TSZ is about to be powered up. Also disclosed are associated embodiments of a system and method for designing such an integrated circuit chip.

Abstract translation: 公开了设计用于在低环境温度下可靠性的集成电路芯片的实施例。 芯片基板可以分为包括至少一个包含一个或多个温度敏感电路的至少一个温度敏感区（TSZ）的区域。 温度传感器可以位于与TSZ相邻的半导体衬底中。 热辐射器可以嵌入在金属布线层中，并在TSZ上方对齐。 温度传感器可以可操作地连接到散热器，并且当TSZ中的温度低于预定阈值温度时，可以触发热辐射器的操作。 此外，片上功率控制系统可以可操作地连接到散热器，使得热辐射器的操作仅在TSZ内的电路即将被加电时触发。 还公开了用于设计这种集成电路芯片的系统和方法的相关实施例。

公开(公告)号：US07937560B2

公开(公告)日：2011-05-03

申请号：US12121292

申请日：2008-05-15

Applicant: Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Sebastian T. Ventrone ,  Keith R. Williams

Inventor： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Sebastian T. Ventrone ,  Keith R. Williams

IPC: G06F15/76 ,  G06F1/00

CPC classification number: G06F9/3867 ,  G06F1/32 ,  G06F1/3287 ,  G06F11/1407 ,  G06F11/1441 ,  Y02D10/171

Abstract: A solution for retaining a logic state of a processor pipeline architecture are disclosed. A comparator is positioned between two stages of the processor pipeline architecture. A storage capacitor is coupled between a storage node of the comparator and a ground to store an output of the early one of the two stages. A reference logic is provided, which has the same value as the output of the early stage. A logic storing and dividing device is coupled between the reference logic and a reference node of the comparator to generate a logic at the reference node, which is a fraction of the reference logic, and to retain a logic state of the information stored on the storage capacitor. Further mechanisms are provided to determine validity of data stored in the logic storing and dividing device.

Abstract translation: 公开了一种用于保留处理器流水线架构的逻辑状态的解决方案。 比较器位于处理器流水线架构的两个阶段之间。 存储电容器耦合在比较器的存储节点和地之间以存储两个阶段的早期阶段的输出。 提供了与早期输出值相同的参考逻辑。 逻辑存储和分配装置耦合在参考逻辑和比较器的参考节点之间，以便在参考节点产生逻辑，该参考节点是参考逻辑的一小部分，并且保留存储在存储器上的信息的逻辑状态 电容器。 提供进一步的机制来确定存储在逻辑存储和分配装置中的数据的有效性。

公开(公告)号：US07916531B2

公开(公告)日：2011-03-29

申请号：US12351872

申请日：2009-01-12

Applicant: Wagdi W. Abadeer ,  Anthony R Bonaccio ,  Jack A Mandelman ,  William R. Tonti ,  Sebastian T Ventrone

Inventor： Wagdi W. Abadeer ,  Anthony R Bonaccio ,  Jack A Mandelman ,  William R. Tonti ,  Sebastian T Ventrone

IPC: G11C11/34

CPC classification number: G11C16/0466

Abstract: In a first aspect, a first apparatus is provided. The first apparatus is a memory element that includes (1) one or more MOSFETs each including a dielectric material having a dielectric constant of about 3.9 to about 25; and (2) control logic coupled to at least one of the one or more MOSFETs. The control logic is adapted to (a) cause the memory element to operate in a first mode to store data; and (b) cause the memory element to operate in a second mode to change a threshold voltage of at least one of the one or more MOSFETs from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects data stored by the memory element when operated in the first mode. Numerous other aspects are provided.

Abstract translation: 在第一方面中，提供了一种第一装置。 第一装置是存储元件，其包括（1）一个或多个MOSFET，每个MOSFET包括具有约3.9至约25的介电常数的电介质材料; 和（2）耦合到所述一个或多个MOSFET中的至少一个的控制逻辑。 控制逻辑适于（a）使存储元件以第一模式操作以存储数据; 和（b）使存储元件在第二模式下操作以将一个或多个MOSFET中的至少一个的阈值电压从原始阈值电压改变到改变的阈值电压，使得改变的阈值电压影响由 存储元件在第一模式下操作。 提供了许多其他方面。

公开(公告)号：US07895459B2

公开(公告)日：2011-02-22

申请号：US11938899

申请日：2007-11-13

Applicant: Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith R. Williams

Inventor： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith R. Williams

IPC: G06F1/00

CPC classification number: G06F1/3203 ,  G06F1/3287 ,  Y02D10/171

Abstract: A design structure for a system and method of predicting power events in intermittent power environments and dispatching computational operations of an integrated circuit accordingly. A power management prediction system includes a controller executing a prediction algorithm, an arrangement of computation circuitry, a non-volatile storage device containing a power requirements log and a power history log, a clock generator, an intermittent power source, and a power monitor circuit. A method of predicting intermittent power events and dispatching computational operations includes: storing power requirements of each computational operation, monitoring the intermittent power source to generate a history log, predicting a subsequent power event based on the history log, retrieving actual power requirements of one or more computational operations, comparing the predicted power event with actual power requirements, determining whether actual power requirements are satisfied, dispatching one or more computational operations that correspond to one or more actual power events, or performing an error recovery operation.

Abstract translation: 一种用于系统的设计结构以及在间歇电力环境中预测电力事件并相应地调度集成电路的计算操作的方法。 功率管理预测系统包括执行预测算法的控制器，计算电路的布置，包含电力需求日志和电力历史记录的非易失性存储装置，时钟发生器，间歇电源和功率监视电路 。 一种预测间歇功率事件和调度计算操作的方法包括：存储每个计算操作的功率需求，监测间歇电源以生成历史日志，根据历史日志预测后续功率事件，检索一个或者 更多的计算操作，将预测功率事件与实际功率需求进行比较，确定是否满足实际功率需求，调度与一个或多个实际功率事件相对应的一个或多个计算操作，或执行错误恢复操作。

公开(公告)号：US20110019819A1

公开(公告)日：2011-01-27

申请号：US12507481

申请日：2009-07-22

Applicant: Kerry Bernstein ,  Sebastian T. Ventrone

Inventor： Kerry Bernstein ,  Sebastian T. Ventrone

IPC: H04K1/02

CPC classification number: H04K3/825 ,  H04K3/42

Abstract: A system is provided for securing information residing on a circuit (e.g., processor). In particular, a system and method is provided for masking electromagnetic interference (EMI) emissions emitting from a circuit using a random noise generator in combination with a low noise amplifier and antenna. The random number generator matches a frequency of a circuit to be protected, and generates a random signal to be superimposed on data. The low noise amplifier receives the random signal from the random number generator, and an antenna receives the random signal from the low noise amplifier and transmits the random signal to mask the data of the circuit to be protected.

Abstract translation: 提供了用于保护驻留在电路（例如，处理器）上的信息的系统。 特别地，提供了一种用于屏蔽使用随机噪声发生器与低噪声放大器和天线组合的从电路发射的电磁干扰（EMI）发射的系统和方法。 随机数发生器匹配要保护的电路的频率，并产生要叠加在数据上的随机信号。 低噪声放大器从随机数发生器接收随机信号，并且天线从低噪声放大器接收随机信号，并发送随机信号以掩蔽要被保护的电路的数据。

公开(公告)号：US07865862B2

公开(公告)日：2011-01-04

申请号：US11937106

申请日：2007-11-08

Applicant: Deanna J. Chou ,  Jesse E. Craig ,  John Sargis, Jr. ,  Daneyand J. Singley ,  Sebastian T. Ventrone

Inventor： Deanna J. Chou ,  Jesse E. Craig ,  John Sargis, Jr. ,  Daneyand J. Singley ,  Sebastian T. Ventrone

IPC: G06F17/50

CPC classification number: G06F9/3836 ,  G06F9/3885

Abstract: A design structure embodied in a machine readable medium used in a design process includes an apparatus for dynamically selecting compiled instructions for execution, the apparatus including an input for receiving static instructions for execution on a first execution unit and receiving dynamic instructions for execution on a second execution unit; and an instruction selection element adapted to evaluate throughput performance of the static instructions and dynamic instructions based on current states of the execution units and select the static instructions or the dynamic instructions for execution at runtime on the first execution unit or the second execution unit, respectively, based on the throughput performance of the instructions.

Abstract translation: 体现在设计过程中使用的机器可读介质中的设计结构包括用于动态选择编译指令进行执行的装置，该装置包括用于接收用于在第一执行单元上执行的静态指令的输入，以及在第二执行单元上接收用于执行的动态指令 执行单位 以及指令选择元件，其适于基于所述执行单元的当前状态来评估所述静态指令和动态指令的吞吐量性能，并分别在所述第一执行单元或所述第二执行单元上的运行时选择所述静态指令或用于执行的所述动态指令 ，基于指令的吞吐量性能。

公开(公告)号：US07791968B2

公开(公告)日：2010-09-07

申请号：US11924955

申请日：2007-10-26

Applicant: Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith R. Williams

Inventor： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith R. Williams

IPC: G11C29/00

CPC classification number: G11C29/50 ,  G11C11/41 ,  G11C29/56 ,  G11C2029/0403 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1203

Abstract: An integrated circuit and a design structure are disclosed. An integrated circuit may comprise: a data retaining device; a partially depleted silicon-on-insulator (PD SOI) device electrically coupled to the data retaining device; and a measurement device coupled to the PD SOI device for measuring a state of the PD SOI device indicating a body voltage thereof, the measuring device being communicatively coupled to a calculating means which determines a history state of a data in the data retaining device based on the measured state of the PD SOI device.

Abstract translation: 公开了集成电路和设计结构。 集成电路可以包括：数据保持装置; 电耦合到数据保持装置的部分耗尽的绝缘体上硅（PD SOI）装置; 以及耦合到所述PD SOI器件的测量装置，用于测量所述PD SOI器件的表示其体电压的状态，所述测量装置通信地耦合到计算装置，所述计算装置基于所述计算装置确定所述数据保持装置中的数据的历史状态 测量PD SOI器件的状态。

公开(公告)号：US07755420B2

公开(公告)日：2010-07-13

申请号：US12196718

申请日：2008-08-22

Applicant: Anthony R. Bonaccio ,  Hayden C. Cranford, Jr. ,  Joseph A. Iadanza ,  Sebastian T. Ventrone ,  Stephen D. Wyatt

Inventor： Anthony R. Bonaccio ,  Hayden C. Cranford, Jr. ,  Joseph A. Iadanza ,  Sebastian T. Ventrone ,  Stephen D. Wyatt

IPC: H03K5/00

CPC classification number: G05F1/46

Abstract: Analog supply for an analog circuit and process for supplying an analog signal to an analog circuit. The analog supply includes a noise filter having a variable resistor, and a control device coupled to adjust the variable resistor. The control device is structured and arranged to set the resistance of the variable resistor to maximize noise filtering and optimize performance of the analog circuit.

Abstract translation: 用于模拟电路的模拟电源和用于向模拟电路提供模拟信号的过程。 模拟电源包括具有可变电阻器的噪声滤波器和耦合以调节可变电阻器的控制装置。 控制装置被构造和布置成设置可变电阻器的电阻以最大化噪声滤波并优化模拟电路的性能。

公开(公告)号：US20100031067A1

公开(公告)日：2010-02-04

申请号：US12183099

申请日：2008-07-31

Applicant: Igor Arsovski ,  Hayden C. Cranford, JR. ,  Sebastian T. Ventrone

Inventor： Igor Arsovski ,  Hayden C. Cranford, JR. ,  Sebastian T. Ventrone

IPC: G06F1/03

CPC classification number: G06F1/03 ,  G06F1/26

Abstract: A proactive noise suppression system and method for a power supply network of an integrated circuit. The system and method include receiving an IC event sequence to a memory element, correlating the IC event sequence to a storage location in a second memory element, the storage location including an anti-noise response signature, and utilizing the anti-noise response signature to proactively generate an anti-noise response in a power supply network in at least a portion of the integrated circuit at about the time of execution of the first IC event sequence. Anti-noise response signatures may be adaptively updated and/or created based on noise measurements made corresponding to execution of an IC event sequence by the integrated circuit.

Abstract translation: 一种用于集成电路的电源网络的主动噪声抑制系统和方法。 该系统和方法包括：向存储元件接收IC事件序列，将IC事件序列与第二存储器元件中的存储位置相关联，存储位置包括抗噪声响应签名，并将抗噪声响应签名 在执行第一IC事件序列时，在集成电路的至少一部分中，主动地在电力供应网络中产生抗噪声响应。 基于通过集成电路执行IC事件序列进行的噪声测量可以自适应地更新和/或创建抗噪声响应签名。