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公开(公告)号：US07146392B2
公开(公告)日：2006-12-05
申请号：US10604178
申请日：2003-06-30
IPC分类号： G06F1/02
CPC分类号： G06F7/588 , H04L9/0869
摘要： A random number generator (10) comprising a plurality of voltage islands (12) on a chip (14), one or more latches (16) located on each of plurality of voltage islands (12), with one or more latches (16) adapted to capture the voltage value of the respective voltage island on which they are located as an input value of one or more latches (16), a control circuit (18) for randomly controlling the state of each of plurality of voltage islands (12) and for capturing an output value for each of one or more latches (16), and a conversion circuit (20) for producing decimal numbers from the output value for each of one or more latches (16). In one embodiment, control circuit (18) includes two or more clocks (30), a multiplexer (32) for each of plurality of voltage islands (12), and an enable circuit (34) for each of plurality of voltage islands (12).
摘要翻译： 一种随机数发生器（10），包括位于芯片（14）上的多个电压岛（12），位于多个电压岛（12）中的每一个上的一个或多个锁存器（16），其中一个或多个锁存器（16） 适于捕获它们所位于的各个电压岛的电压值作为一个或多个锁存器（16）的输入值，用于随机地控制多个电压岛（12）中的每一个的状态的控制电路（18） 并且用于捕获一个或多个锁存器（16）中的每一个的输出值，以及用于根据一个或多个锁存器（16）中的每一个的输出值产生十进制数的转换电路（20）。 在一个实施例中，控制电路（18）包括两个或多个时钟（30），用于多个电压岛（12）中的每一个的复用器（32）和用于多个电压岛（12）中的每一个的使能电路（34） ）。
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公开(公告)号：US07103320B2
公开(公告)日：2006-09-05
申请号：US10249568
申请日：2003-04-19
申请人： Kenneth J Goodnow , Riyon W Harding , Charles J Masenas , Jason M Norman , Sebastian T Ventrone
发明人： Kenneth J Goodnow , Riyon W Harding , Charles J Masenas , Jason M Norman , Sebastian T Ventrone
CPC分类号： H04B1/38
摘要： A communication system (8) for transmitting data between cores (10) embedded in an integrated circuit on a silicon chip (12). Communication system (8) includes transmitter circuitry (24) for wirelessly transmitting data between cores (10) and receiver circuitry (26) for wirelessly receiving the transmission of data from other cores. Both transmitter circuitry (24) and receiver circuitry (26) may include of a phase-locked loop circuit (28, 30) having a voltage-controlled oscillator (36). Each core (10) may transmit and receive data on a unique frequency with respect to other cores embedded in an integrated circuit on a silicon chip (12) or transmit and receive data on the same frequency as other cores embedded in an integrated circuit on a silicon chip (12). Groups of cores (17) may share transmitter and receiver circuitry (24 and 26).
摘要翻译： 一种用于在嵌入在硅芯片（12）上的集成电路中的核心（10）之间传输数据的通信系统（8）。 通信系统（8）包括用于在核心（10）和接收机电路（26）之间无线传输数据的发射机电路（24），用于无线地接收来自其他核心的数据传输。 发射机电路（24）和接收机电路（26）可以包括具有压控振荡器（36）的锁相环电路（28,30）。 每个核心（10）可以相对于嵌入在硅芯片（12）上的集成电路中的其它核心的唯一频率发送和接收数据，或者发送和接收与嵌入在集成电路中的其他核心相同的频率的数据 硅芯片（12）。 核心组（17）可以共享发射机和接收机电路（24和26）。
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公开(公告)号：US07249279B2
公开(公告)日：2007-07-24
申请号：US10707304
申请日：2003-12-04
IPC分类号： G06K11/00
CPC分类号： G06F8/65
摘要： Operating code fixes are supplied to multiple processors utilizing the same operating code by storing the correction code fixes in a central RAM, and distributing the code fixes over a dedicated code fix bus to a local cache for each processor. The first processor encountering a code fix requests the code fix from the RAM, which then distributes the code fix over the code fix bus to all of the local caches which are automatically updated with the new code. The system is particularly applicable to an integrated circuit having multiple processors fabricated on a chip, wherein the RAM is on-chip and is connected to an off-chip EEPROM that loads corrected code fixes to the on-chip RAM at power-up.
摘要翻译： 通过将修正代码修正存储在中央RAM中并将专用代码修复总线上的代码修正分配给每个处理器的本地高速缓存，将操作代码修复程序提供给使用相同操作代码的多个处理器。 遇到代码修复的第一个处理器从RAM请求代码修复，然后将代码修复总线分配给所有使用新代码自动更新的本地缓存。 该系统特别适用于具有在芯片上制造的多个处理器的集成电路，其中RAM是芯片上的，并且连接到片外EEPROM，其在加电时将校正的代码固定件加载到片上RAM。
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公开(公告)号：US20080212977A1
公开(公告)日：2008-09-04
申请号：US11772378
申请日：2007-07-02
申请人： Gary R. Doyle , Kenneth J. Goodnow , Riyon W. Harding , Francis A. Kampf , Jason M. Norman , Sebastian T. Ventrone
发明人： Gary R. Doyle , Kenneth J. Goodnow , Riyon W. Harding , Francis A. Kampf , Jason M. Norman , Sebastian T. Ventrone
IPC分类号： H04B10/00
CPC分类号： G02B6/43
摘要： An optical transmission method. Signal transmissions between cores of an integrated circuit are performed. Each signal transmission is between two cores of a different pair of cores of the integrated circuit. Each signal transmission includes transmission of an optical signal in the visible or infrared portion of the electromagnetic spectrum at a wavelength that is specific to each different pair of cores and is a different wavelength for each different pair of cores. There is no overhead for decoding or arbitration in preforming the signal transmissions that would otherwise exist if a same wavelength for the optical signals were permitted for pairs of cores of the different pairs of cores.
摘要翻译： 光传输方法。 执行集成电路的核心之间的信号传输。 每个信号传输在集成电路的不同核心的两个核之间。 每个信号传输包括以对于每个不同的核对特定的波长的电磁光谱的可见光或红外部分中的光信号的传输，并且对于每个不同的一对核心是不同的波长。 如果对于不同核心对的核对允许相同的光信号波长，则在进行信号传输时，没有解码或仲裁的开销。
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公开(公告)号：US07248838B2
公开(公告)日：2007-07-24
申请号：US11410829
申请日：2006-04-24
申请人： Kenneth J. Goodnow , Riyon W. Harding , Charles J. Masenas , Jason M. Norman , Sebastian T. Ventrone
发明人： Kenneth J. Goodnow , Riyon W. Harding , Charles J. Masenas , Jason M. Norman , Sebastian T. Ventrone
CPC分类号： H04B1/38
摘要： A communication system for transmitting data between cores embedded in an integrated circuit on a silicon chip. Communication system includes transmitter circuitry for wirelessly transmitting data between cores and receiver circuitry for wirelessly receiving the transmission of data from other cores. Both transmitter circuitry and receiver circuitry may include of a phase-locked loop circuit having a voltage-controlled oscillator. Each core may transmit and receive data on a unique frequency with respect to other cores embedded in an integrated circuit on a silicon chip or transmit and receive data on the same frequency as other cores embedded in an integrated circuit on a silicon chip. Groups of cores may share transmitter and receiver circuitry.
摘要翻译： 一种用于在嵌入在硅芯片上的集成电路中的核之间传输数据的通信系统。 通信系统包括用于在核心和接收机电路之间无线地传输数据的发射机电路，用于无线地接收来自其他核的数据传输。 发射机电路和接收机电路都可以包括具有压控振荡器的锁相环电路。 每个核心可以相对于嵌入在硅芯片上的集成电路中的其它核心以独特的频率发送和接收数据，或者以与嵌入在硅芯片上的集成电路中的其它芯片相同的频率发送和接收数据。 核心组可以共享发射机和接收机电路。
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公开(公告)号：US07286770B2
公开(公告)日：2007-10-23
申请号：US10604410
申请日：2003-07-18
申请人： Gary R. Doyle , Kenneth J. Goodnow , Riyon W. Harding , Francis A. Kampf , Jason M. Norman , Sebastian T. Ventrone
发明人： Gary R. Doyle , Kenneth J. Goodnow , Riyon W. Harding , Francis A. Kampf , Jason M. Norman , Sebastian T. Ventrone
IPC分类号： H04B10/00
CPC分类号： G02B6/43
摘要： Disclosed is an integrated circuit comprising a plurality of cores attached to at least one transmitter and receiver, an optical transmission network embedded within the wire levels of the integrated circuit, and wherein the transmitter and receivers send and receive data on the network. Also disclosed is a method of transmitting signals within an integrated circuit comprising an integrated circuit comprising a plurality of cores and optical paths, selecting an optical path from the plurality of optical paths for transmitting data, and transmitting the data on the selected optical path. Also disclosed is an integrated circuit comprising an optical transmission network, a plurality of cores, and a plurality of controllers, all three being operatively attached to each other.
摘要翻译： 公开了一种集成电路，其包括附接到至少一个发射机和接收机的多个核心，嵌入在集成电路的有线电平内的光传输网络，并且其中发射机和接收机在网络上发送和接收数据。 还公开了一种在包括多个核心和光路的集成电路的集成电路内传输信号的方法，从多个光路中选择用于发送数据的光路，以及在所选择的光路上发送数据。 还公开了一种集成电路，其包括光传输网络，多个核心和多个控制器，所有三个可操作地彼此连接。
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