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公开(公告)号：US07103320B2
公开(公告)日：2006-09-05
申请号：US10249568
申请日：2003-04-19
申请人： Kenneth J Goodnow , Riyon W Harding , Charles J Masenas , Jason M Norman , Sebastian T Ventrone
发明人： Kenneth J Goodnow , Riyon W Harding , Charles J Masenas , Jason M Norman , Sebastian T Ventrone
CPC分类号： H04B1/38
摘要： A communication system (8) for transmitting data between cores (10) embedded in an integrated circuit on a silicon chip (12). Communication system (8) includes transmitter circuitry (24) for wirelessly transmitting data between cores (10) and receiver circuitry (26) for wirelessly receiving the transmission of data from other cores. Both transmitter circuitry (24) and receiver circuitry (26) may include of a phase-locked loop circuit (28, 30) having a voltage-controlled oscillator (36). Each core (10) may transmit and receive data on a unique frequency with respect to other cores embedded in an integrated circuit on a silicon chip (12) or transmit and receive data on the same frequency as other cores embedded in an integrated circuit on a silicon chip (12). Groups of cores (17) may share transmitter and receiver circuitry (24 and 26).
摘要翻译： 一种用于在嵌入在硅芯片（12）上的集成电路中的核心（10）之间传输数据的通信系统（8）。 通信系统（8）包括用于在核心（10）和接收机电路（26）之间无线传输数据的发射机电路（24），用于无线地接收来自其他核心的数据传输。 发射机电路（24）和接收机电路（26）可以包括具有压控振荡器（36）的锁相环电路（28,30）。 每个核心（10）可以相对于嵌入在硅芯片（12）上的集成电路中的其它核心的唯一频率发送和接收数据，或者发送和接收与嵌入在集成电路中的其他核心相同的频率的数据 硅芯片（12）。 核心组（17）可以共享发射机和接收机电路（24和26）。
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2.发明授权
公开(公告)号：US5903230A
公开(公告)日：1999-05-11
申请号：US899205
申请日：1997-07-23
申请人： Charles J. Masenas
发明人： Charles J. Masenas
CPC分类号： G06T9/005 , H03M7/3086
摘要： A data processing system having a compression and decompression apparatus based on the Lempel-Ziv algorithm. The compression apparatus includes an array section having a circular history CAM unit for receiving and storing one or more data elements and a coding unit for determining whether received data elements previously have been stored in the history CAM unit and are a candidate for compression. If a received data element matches at least one of the stored data elements, a PS logic section determines whether there is the presence of a string. An encoding section identifies the address of the matching stored data element in a string and the length of the string. The compression apparatus generates a compression token comprising an identification of whether a data element is compressed, the length of the coded data within a plurality of predetermined data length categories and an address. The compression apparatus uses a particular hardware implementation of the PS logic section.
摘要翻译： 一种具有基于Lempel-Ziv算法的压缩和解压缩装置的数据处理系统。 压缩装置包括具有圆形历史CAM单元的阵列部分，用于接收和存储一个或多个数据元素，以及编码单元，用于确定接收的数据元素是否已经存储在历史CAM单元中，并且是用于压缩的候选。 如果接收的数据元素与所存储的数据元素中的至少一个匹配，则PS逻辑部分确定是否存在字符串。 编码部分标识字符串中匹配的存储数据元素的地址和字符串的长度。 压缩装置生成压缩令牌，其包括数据元素是否被压缩的标识，多个预定数据长度类别内的编码数据的长度以及地址。 压缩装置使用PS逻辑部分的特定硬件实现。
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公开(公告)号：US5694032A
公开(公告)日：1997-12-02
申请号：US619447
申请日：1996-03-19
IPC分类号： G05F3/26
CPC分类号： G05F3/262
摘要： A circuit for delivering an accurate reference current independent of operating frequency that is implementable on-chip and that is relatively insensitive to process and temperature variations. A frequency source controls a rate of charge transfer via a switched capacitor to generate a constant current over different frequencies. A complimentary doped FET provides a band gap voltage imposed over a known resistance to generate the output current.
摘要翻译： 用于传递独立于片上可实现且对于过程和温度变化相对不敏感的工作频率的精确参考电流的电路。 频率源通过开关电容器控制电荷转移速率，以在不同频率上产生恒定电流。 补充掺杂的FET提供施加在已知电阻上的带隙电压以产生输出电流。
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公开(公告)号：US5534790A
公开(公告)日：1996-07-09
申请号：US227162
申请日：1994-04-13
IPC分类号： H03K17/16
CPC分类号： H03K17/163
摘要： A current transition rate control circuit is provided, comprising first and second data inputs; first and second charge/discharge circuits for receiving the first and second data inputs; a first reference voltage circuit for sending a first control signal and a second reference voltage circuit for sending a second control signal to, respectively, the first and second charge/discharge circuits; and first and second output transistors coupled, respectively, to the outputs of the first and second charge/discharge circuits. The circuit controls the switching speed of the output transistors to minimize current spikes on the output. The circuit may include a pre-driver circuit for (i) receiving a single data input and outputting the first and second data inputs, and (ii) receiving a circuit disabling signal and placing the circuit in a high impedance state which turns off both of the output transistors. A test circuit is also provided for deactivating the first and second data inputs and for shutting off current flow in the first and second reference voltage circuits so that leakage current in the circuit may be measured.
摘要翻译： 提供了一种电流转换速率控制电路，包括第一和第二数据输入; 用于接收第一和第二数据输入的第一和第二充电/放电电路; 用于发送第一控制信号的第一参考电压电路和用于分别向第一和第二充电/放电电路发送第二控制信号的第二参考电压电路; 以及分别耦合到第一和第二充电/放电电路的输出的第一和第二输出晶体管。 电路控制输出晶体管的开关速度，以最小化输出端的电流尖峰。 电路可以包括用于（i）接收单个数据输入并输出第一和第二数据输入的预驱动器电路，以及（ii）接收电路禁用信号并将电路置于高阻抗状态， 输出晶体管。 还提供测试电路用于停用第一和第二数据输入并关闭第一和第二参考电压电路中的电流，从而可以测量电路中的漏电流。
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公开(公告)号：US6011423A
公开(公告)日：2000-01-04
申请号：US862896
申请日：1997-05-23
IPC分类号： H03K17/0416 , H03K19/013 , H03K17/56
CPC分类号： H03K19/013 , H03K17/04166
摘要： A voltage boosting circuit for an "H-driver," providing for each "pull-up" switch in the H-driver a switching shunt that charges a capacitor from a supply voltage when the "pull-up" switch is open and couples the capacitor directly to the write head when the "pull-up" switch is closed. The side of the capacitor which is not directly coupled to the write head is coupled to the data signal (or its inverse, in the case of the capacitor for the otherwise identical circuit serving the parallel half of the "H-driver") through a buffer which sets the voltage at the signal level (or its inverse), thereby dumping the charge to the write head and elevating the voltage of the write head significantly above the supply voltage. The identical circuit serving the parallel half of the "H-driver" similarly boosts the negative going transition voltage.
摘要翻译： 用于“H驱动器”的升压电路为H驱动器中的每个“上拉”开关提供一个开关分流器，当“上拉”开关断开时，电源从电源电压充电，并将 当“上拉”开关闭合时，电容器直接连接到写入头。 不直接耦合到写头的电容器的一侧耦合到数据信号（或者在与“H驱动器”的平行半部分相同的电路的电容器的情况下，其反相）通过 缓冲器将电压设置在信号电平（或其反相），从而将电荷转移到写入头，并将写入头的电压显着地高于电源电压。 用于“H驱动器”的并行半部分的相同电路同样提高了负向转变电压。
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公开(公告)号：US5771010A
公开(公告)日：1998-06-23
申请号：US408577
申请日：1995-03-22
申请人： Charles J. Masenas
发明人： Charles J. Masenas
CPC分类号： G06T9/005 , H03M7/3086
摘要： A data processing system having a compression and decompression apparatus based on the Lempel-Ziv algorithm. The compression apparatus includes an array section having a circular history CAM unit for receiving and storing one or more data elements and a coding unit for determining whether received data elements previously have been stored in the history CAM unit and are a candidate for compression. If a received data element matches at least one of the stored data elements, a PS logic section determines whether there is the presence of a string. An encoding section identifies the address of the matching stored data element in a string and the length of the string. The compression apparatus generates a compression token comprising an identification of whether a data element is compressed, the length of the coded data within a plurality of predetermined data length categories and an address. The compression apparatus uses a particular hardware implementation of the PS logic section.
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公开(公告)号：US5629650A
公开(公告)日：1997-05-13
申请号：US593755
申请日：1996-01-29
CPC分类号： H03L7/0891 , H03L7/099 , H03L2207/06
摘要： According to the preferred embodiment, a self-biased phase-locked loop is provided that overcomes the limitations of the prior art bias methods and apparatus. In general, a self-biased current controlled semiconductor device, typically a current controlled oscillator, is self biased by the use of a first feedback path, typically provided by a phase-locked loop, where the feedback path provides a control current for controlling the current controlled device. A second feedback path, typically a pair current mirrors, serves as a bias loop having unity gain. The bias loop provides a bias current that is responsive to the control current. This device has the advantage of being self biasing, thus no other biasing circuitry is required.
摘要翻译： 根据优选实施例，提供克服现有技术偏压方法和装置的限制的自偏置锁相环。 通常，自偏置电流控制半导体器件（通常为电流控制振荡器）通过使用通常由锁相环路提供的第一反馈路径自偏置，其中反馈路径提供控制电流以控制 电流控制装置 第二反馈路径（通常为一对电流镜）用作具有单位增益的偏置环路。 偏置环路提供响应于控制电流的偏置电流。 该器件具有自偏置的优点，因此不需要其它偏置电路。
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公开(公告)号：US4555776A
公开(公告)日：1985-11-26
申请号：US369970
申请日：1982-04-19
IPC分类号： H03K19/018 , G11C11/414 , G11C11/416 , G11C7/00
CPC分类号： G11C11/416
摘要： A voltage balancing circuit, particularly suitable for bipolar memory arrays producing small signals, is provided which includes first and second conductive lines, a point of reference potential, a first device disposed between the first conductive line and the point of reference potential, a second device disposed between the second conductive line and the point of reference potential, first and second transistors, first means for coupling the first line through the first transistor to the second line, second means for coupling the second line through the second transistor to the first line, and means for supplying substantially equal signals to the control electrodes of the first and second transistors. When used in a memory array, the conductive lines are the bit/sense lines, the point of reference potential is a bit/sense line reference voltage and the equal signals for the control electrodes of the transistors are provided in response to a signal from a bit decoder.
摘要翻译： 提供了特别适用于产生小信号的双极性存储器阵列的电压平衡电路，其包括第一和第二导线，参考点电位，设置在第一导线与参考电位之间的第一器件，第二器件 设置在第二导线和参考点之间的第一和第二晶体管，用于将第一线通过第一晶体管耦合到第二线的第一装置，用于将第二线通过第二晶体管耦合到第一线的第二装置， 以及用于向第一和第二晶体管的控制电极提供基本相等的信号的装置。 当在存储器阵列中使用时，导线是位/检测线，参考点电位是位/检测线参考电压，并且响应于来自于...的信号提供晶体管的控制电极的相等信号 位解码器。
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公开(公告)号：US4404662A
公开(公告)日：1983-09-13
申请号：US280396
申请日：1981-07-06
IPC分类号： G11C11/414 , G11C11/416 , G11C11/40
CPC分类号： G11C11/416
摘要： A memory system is provided having an array of cells, each of which may include first and second cross-coupled inverting NPN transistors and first and second PNP transistors for injecting charge into the first and second inverting transistors. A first bit/sense line of a bit/sense line pair is connected to the emitter of the first inverting transistor and a second bit/sense line of the pair is connected to the emitter of the second inverting transistor and a common word line is connected to the emitters of the first and second charge injecting transistors. To read a selected cell, all cells of the array are discharged through the word lines, the pair of bit/sense lines connected to the selected cell are electrically floated or isolated and the word line connected to the selected cell is energized by a word driver. The signal developed in the bit/sense lines connected to the selected cell is detected while the word line connected to the selected cell is being energized by the word driver.
摘要翻译： 提供了具有单元阵列的存储器系统，每个单元可以包括第一和第二交叉耦合反相NPN晶体管，以及用于将电荷注入第一和第二反相晶体管的第一和第二PNP晶体管。 位/检测线对的第一位/检测线连接到第一反相晶体管的发射极，并且该对的第二位/感测线连接到第二反相晶体管的发射极，并且连接公共字线 到第一和第二电荷注入晶体管的发射极。 为了读取所选择的单元，阵列的所有单元通过字线放电，连接到所选单元的一对位/检测线被浮置或隔离，并且连接到所选单元的字线由字驱动器 。 在连接到所选择的单元的字线被字驱动器激励的同时检测连接到所选单元的位/检测线中产生的信号。
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公开(公告)号：US07088190B2
公开(公告)日：2006-08-08
申请号：US10709811
申请日：2004-05-28
IPC分类号： H03B5/24
CPC分类号： H03K3/012 , H03K3/0315
摘要： A voltage-controlled oscillator (VCO) comprising an odd number of delay stage circuits. Each delay stage circuit operates between supply voltages VDD and VSS (VDD>VSS) and comprises (1) an input node, (2) an output node, (3) an inverting circuit, and (4) an electric discharge path coupling the output node to VSS. The electric discharge path includes a switch circuit and a resistance adjusting circuit electrically coupled in series between the output node and VSS. In response to an input signal rising at the input node, the inverting circuit decreases an output signal at the output node, and the electric discharge path opens to help pull the output signal down faster. In response to an input signal falling at the input node, the inverting circuit increases the output signal at the output node, and the electric discharge path closes to minimize its own effect.
摘要翻译： 包括奇数个延迟级电路的压控振荡器（VCO）。 每个延迟级电路在电源电压VDD和VSS（VDD> VSS）之间工作，并且包括（1）输入节点，（2）输出节点，（3）反相电路，以及（4）将输出 节点到VSS。 放电路径包括在输出节点和VSS之间串联电耦合的开关电路和电阻调节电路。 响应于在输入节点处上升的输入信号，反相电路减小输出节点处的输出信号，并且放电路径打开以帮助较快地拉出输出信号。 响应于在输入节点处的输入信号，反相电路增加输出节点处的输出信号，并且放电路径关闭以最小化其自身的效果。
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