VERIFYING NON-DETERMINISTIC BEHAVIOR OF A DESIGN UNDER TEST
    1.
    发明申请
    VERIFYING NON-DETERMINISTIC BEHAVIOR OF A DESIGN UNDER TEST 有权
    验证设计的非确定行为

    公开(公告)号:US20090210837A1

    公开(公告)日:2009-08-20

    申请号:US12034161

    申请日:2008-02-20

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5022

    摘要: The invention generally relates to design verification, and more particularly to verification of non-deterministic behavior of a design under test. A method includes predicting a plurality of behaviors of a design under test (DUT), and forking respective verification tasks for each one of the plurality of behaviors. The method further includes verifying an actual behavior of the DUT with each of the verification tasks, and terminating a respective one of the verification tasks when the actual behavior of the DUT does not conform to the respective one of the verification tasks.

    摘要翻译: 本发明通常涉及设计验证,更具体地涉及对被测设计的非确定性行为的验证。 一种方法包括:对被测设计(DUT)的多个行为进行预测,以及针对所述多个行为中的每一个划分相应的验证任务。 该方法还包括:当DUT的实际行为不符合相应的一个验证任务时,通过每个验证任务验证DUT的实际行为,并终止相应的一个验证任务。

    Simulation testing of digital logic circuit designs
    2.
    发明授权
    Simulation testing of digital logic circuit designs 有权
    数字逻辑电路设计仿真测试

    公开(公告)号:US07251794B2

    公开(公告)日:2007-07-31

    申请号:US10904056

    申请日:2004-10-21

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5031

    摘要: A method and system for testing a circuit design. The method including generating a simulation model of the circuit design, the circuit design comprising one or more source latches, one or more destination latches and a logic function connected between the source latches and the destination latches; generating a modified simulation model of the simulation model by inserting random skew between an output of each source latch and an input of the logic function only in asynchronous data paths between the source latches and the destination latches of the simulation model; and running the modified simulation model.

    摘要翻译: 一种用于测试电路设计的方法和系统。 该方法包括生成电路设计的仿真模型,电路设计包括一个或多个源锁存器,一个或多个目标锁存器和连接在源锁存器和目的地锁存器之间的逻辑功能; 通过在每个源锁存器的输出和逻辑功能的输入之间插入随机偏差仅在模拟模型的源锁存器和目标锁存器之间的异步数据路径中来产生模拟模型的修改的仿真模型; 并运行修改后的仿真模型。

    Optimistic transmission flow control including receiver data discards upon inadequate buffering condition
    3.
    发明授权
    Optimistic transmission flow control including receiver data discards upon inadequate buffering condition 失效
    包括接收机数据的乐观传输流量控制在缓冲条件不足时丢弃

    公开(公告)号:US06480897B1

    公开(公告)日:2002-11-12

    申请号:US08998965

    申请日:1997-12-29

    IPC分类号: G06F1516

    CPC分类号: G06F15/17368

    摘要: A program product for a message processing system in which messages are transmitted from source nodes to destination nodes. A transmission flow control technique is disclosed in which the source node optimistically sends control information and a data portion of a message, and wherein a destination node discards the data portion of the message if it is unable to accommodate it. The destination node, however, retains enough of the control information to identify the message to the source node, and when the destination node is subsequently able to accommodate the data portion, the destination node issues a request to the source node to retransmit the data portion of the message. Discarding of one message is followed by discards of sequential messages, until the destination node is able to accommodate the data portions of messages. The flow control technique disclosed herein is used, for example, in an environment where buffers are posted to accommodate messages at the destination node, and is particularly suited for conditions arising in multi-tasking systems where the destination node is generally assumed to be prepared to accommodate data, however, if not prepared, is likely not prepared for long periods of time.

    摘要翻译: 用于消息处理系统的程序产品,其中消息从源节点传送到目的地节点。 公开了一种传输流控制技术,其中源节点乐观地发送消息的控制信息和数据部分,并且其中目的地节点丢弃该消息的数据部分,如果它不能容纳该消息。 然而,目的地节点保留足够的控制信息以识别到源节点的消息,并且当目的地节点随后能够容纳数据部分时,目的地节点向源节点发出请求以重新发送数据部分 的消息。 丢弃一个消息之后是顺序消息的丢弃,直到目标节点能够容纳消息的数据部分。 本文公开的流控制技术例如在缓冲器被张贴以适应目的地节点处的消息的环境中使用,并且特别适用于通常假定目的地节点准备准备的多任务系统中出现的条件 容纳数据,但如果没有准备,很可能没有准备好长时间。

    Method and apparatus for reducing data expansion during data compression
    4.
    发明授权
    Method and apparatus for reducing data expansion during data compression 有权
    用于在数据压缩期间减少数据扩展的方法和装置

    公开(公告)号:US06281816B1

    公开(公告)日:2001-08-28

    申请号:US09379864

    申请日:1999-08-24

    申请人: Francis A. Kampf

    发明人: Francis A. Kampf

    IPC分类号: H03M700

    CPC分类号: H03M7/30 G06T9/005 H03M7/3086

    摘要: A method and apparatus for reducing data expansion during data compression are provided that allow the coding scheme used to compress data to be swapped between two or more coding schemes. Specifically, a coding window is provided that holds data to be compressed, and the compression potential of data entering or exiting the coding window is calculated. When a first threshold compression potential sum of data entering the window is reached, the coding scheme used to compress the data within the coding window is swapped from one coding scheme to another. A new compression potential sum is set based upon the compression potential of data exiting the window. The compression potential sum comprises a running total of the compression potential of data entering the coding window; and the coding scheme used to compress data within the coding window is swapped from one coding scheme to another when the compression potential sum reaches a first predetermined value. Preferably the first predetermined value is programmable and is related to the bit cost required to swap back and forth between coding schemes. The two preferred coding schemes are ALDC Lempel-Ziv 1 coding and a pass-through coding scheme wherein raw data is passed unencoded. A coding window circuit also is provided that allows analysis of the compression potential of data in accordance with the above method.

    摘要翻译: 提供一种用于在数据压缩期间减少数据扩展的方法和装置,其允许用于压缩在两个或多个编码方案之间交换的数据的编码方案。 具体地说,提供一个保存要压缩的数据的编码窗口,并且计算进入或退出编码窗口的数据的压缩电位。 当达到进入窗口的数据的第一阈值压缩潜力和时,用于压缩编码窗口内的数据的编码方案从一个编码方案交换到另一编码方案。 基于离开窗口的数据的压缩电位设置新的压缩电位和。 压缩电位和包括进入编码窗口的数据的压缩电位的运行总和; 并且当压缩电位和达到第一预定值时,用于压缩编码窗口内的数据的编码方案从一个编码方案交换到另一编码方案。 优选地,第一预定值是可编程的,并且与编码方案之间来回切换所需的位成本相关。 两个优选的编码方案是ALDC Lempel-Ziv 1编码和其中原始数据未经编码的传递编码方案。 还提供一种编码窗口电路,其允许根据上述方法分析数据的压缩电位。

    Adaptive lossless data compression method for compression of color image data
    5.
    发明授权
    Adaptive lossless data compression method for compression of color image data 有权
    用于压缩彩色图像数据的自适应无损数据压缩方法

    公开(公告)号:US08238677B2

    公开(公告)日:2012-08-07

    申请号:US12044297

    申请日:2008-03-07

    IPC分类号: G06K9/00 G06K9/36 G06K9/46

    摘要: An adaptive lossless data compression method for compression of color image data in a data processing system. The method includes comparing a plurality of components of a plurality of adjacent pixels in a digital image, calculating spatial differences between the plurality of adjacent pixels, encoding the spatial differences and recording the encoded spatial differences, formatting an image file representing the digital image into byte streams based on bit significance, and compressing, independently, the byte streams associated with each bit significance of the encoded spatial differences.

    摘要翻译: 一种用于在数据处理系统中压缩彩色图像数据的自适应无损数据压缩方法。 该方法包括比较数字图像中的多个相邻像素的多个分量,计算多个相邻像素之间的空间差异,编码空间差异并记录编码的空间差异,将表示数字图像的图像文件格式化为字节 基于比特重要性的流,并且独立地压缩与编码的空间差异的每个比特重要性相关联的字节流。

    Circuit design verification
    6.
    发明授权
    Circuit design verification 失效
    电路设计验证

    公开(公告)号:US07480607B2

    公开(公告)日:2009-01-20

    申请号:US11383299

    申请日:2006-05-15

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5022

    摘要: A digital circuit simulation method. The method starts with a digital circuit design which includes: a first source latch, a destination latch, a logic cone, a first WAM circuit electrically coupling an output of the first source latch to a first input of the logic cone, and a WAGG circuit electrically coupling an output of the logic cone and an input of the first source latch. Then, a zero-delay simulation is performed in which if a first situation of (a) the first WAM circuit entering an uncertainty state in which the first WAM circuit generates a random value of 1 or 0 at the first input of the logic cone, (b) the logic cone being vulnerable to a positive glitch, and (c) the output of the logic cone being at logic 0, the WAGG circuit generates a random value of 0 or 1 at the input of the destination latch.

    摘要翻译: 数字电路仿真方法。 该方法从数字电路设计开始,其包括:第一源锁存器,目的地锁存器,逻辑锥,将第一源锁存器的输出电耦合到逻辑锥的第一输入端的第一WAM电路,以及WAGG电路 电耦合逻辑锥的输出和第一源锁存器的输入。 然后,执行零延迟模拟,其中如果(a)第一WAM电路进入不确定状态的第一情况,其中第一WAM电路在逻辑锥的第一输入处产生1或0的随机值, (b)逻辑锥体容易受到正的毛刺影响,并且(c)逻辑锥体的输出为逻辑0,WAGG电路在目的地锁存器的输入处产生0或1的随机值。

    Automated simulation testbench generation for serializer/deserializer datapath systems
    7.
    发明授权
    Automated simulation testbench generation for serializer/deserializer datapath systems 有权
    串行器/解串器数据路径系统的自动仿真测试平台生成

    公开(公告)号:US07444258B2

    公开(公告)日:2008-10-28

    申请号:US11275035

    申请日:2005-12-05

    IPC分类号: G01R31/00 G06F19/00

    CPC分类号: G06F17/5022 G01R31/318314

    摘要: Embodiments herein present a method for automated simulation testbench generation for serializer/deserializer datapath systems. The method provides a database of transactors for generating and checking data within the datapath system, wherein the transactors are adaptable to arbitrary configurations of the datapath system. The database is provided with a single set of transactors per core. Next, the method automatically selects one set of transactors from the database for inclusion into the simulation testbenches. Following this, the method maps the first datapath and the second datapath through the datapath system by interconnecting the selected set of the transactors with the datapath system. The method further comprises setting control pins on the cores to facilitate propagation of the data through the cores of the datapath system. Subsequently, the control pins are traced to input ports and control registers.

    摘要翻译: 本文的实施例提供了一种用于串行器/解串器数据路径系统的自动化仿真测试台生成的方法。 该方法提供用于生成和检查数据路径系统内的数据的事务处理器的数据库,其中事务处理器适用于数据通路系统的任意配置。 数据库提供了每个核心单个事务处理器集合。 接下来,该方法自动从数据库中选择一组事务处理器,以便包含在仿真测试台中。 接下来,该方法通过将所选择的一组事务处理器与数据路径系统相互连接,通过数据路径系统映射第一个数据路径和第二个数据路径。 该方法还包括设置核上的控制引脚以便于数据通过数据路径系统的核心的传播。 随后,控制引脚被跟踪到输入端口和控制寄存器。

    FIBER OPTIC TRANSMISSION LINES ON AN SOC
    8.
    发明申请
    FIBER OPTIC TRANSMISSION LINES ON AN SOC 审中-公开
    光纤光纤传输线

    公开(公告)号:US20080212977A1

    公开(公告)日:2008-09-04

    申请号:US11772378

    申请日:2007-07-02

    IPC分类号: H04B10/00

    CPC分类号: G02B6/43

    摘要: An optical transmission method. Signal transmissions between cores of an integrated circuit are performed. Each signal transmission is between two cores of a different pair of cores of the integrated circuit. Each signal transmission includes transmission of an optical signal in the visible or infrared portion of the electromagnetic spectrum at a wavelength that is specific to each different pair of cores and is a different wavelength for each different pair of cores. There is no overhead for decoding or arbitration in preforming the signal transmissions that would otherwise exist if a same wavelength for the optical signals were permitted for pairs of cores of the different pairs of cores.

    摘要翻译: 光传输方法。 执行集成电路的核心之间的信号传输。 每个信号传输在集成电路的不同核心的两个核之间。 每个信号传输包括以对于每个不同的核对特定的波长的电磁光谱的可见光或红外部分中的光信号的传输,并且对于每个不同的一对核心是不同的波长。 如果对于不同核心对的核对允许相同的光信号波长,则在进行信号传输时,没有解码或仲裁的开销。