公开(公告)号：US09472479B2

公开(公告)日：2016-10-18

申请号：US14608537

申请日：2015-01-29

Applicant: CORNING INCORPORATED

Inventor： Satish Chandra Chaparala ,  Scott Christopher Pollard

IPC: H01L21/00 ,  H01L23/15 ,  H01L23/00 ,  H05K1/02 ,  H05K1/18 ,  H01L23/498

CPC classification number: H01L23/49833 ,  H01L21/4857 ,  H01L23/15 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15788 ,  H05K1/0201 ,  H05K1/181 ,  H05K2201/068 ,  H01L2924/00

Abstract: Methods and apparatus are provide for an interposer for interconnecting one or more semiconductor chips with an organic substrate in a semiconductor package, the interposer including: a first glass substrate having first and second opposing major surfaces, the first glass substrate having a first coefficient of thermal expansion (CTE1); a second glass substrate having first and second opposing major surfaces, the second glass substrate having a second coefficient of thermal expansion (CTE2); and an interface disposed between the first and second glass substrates and joining the second major surface of the first glass substrate to the first major surface of the second glass substrate, where CTE1 is less than CTE2, the first major surface of the first glass substrate operates to engage the one or more semiconductor chips, and the second major surface of the second glass substrate operates to engage the organic substrate.

Abstract translation: 提供了用于将一个或多个半导体芯片与半导体封装中的有机衬底互连的插入件的方法和装置，所述插入器包括：具有第一和第二相对主表面的第一玻璃衬底，所述第一玻璃衬底具有第一热导率 扩展（CTE1）; 具有第一和第二相对主表面的第二玻璃基板，所述第二玻璃基板具有第二热膨胀系数（CTE2）; 以及设置在第一和第二玻璃基板之间并且将第一玻璃基板的第二主表面接合到第二玻璃基板的第一主表面的接口，其中CTE1小于CTE2，第一玻璃基板的第一主表面操作 以接合一个或多个半导体芯片，并且第二玻璃基板的第二主表面操作以接合有机基板。

公开(公告)号：US09917045B2

公开(公告)日：2018-03-13

申请号：US15287163

申请日：2016-10-06

Applicant: CORNING INCORPORATED

Inventor： Satish Chandra Chaparala ,  Scott Christopher Pollard

IPC: H01L21/00 ,  H01L23/498 ,  H01L23/15 ,  H01L23/00 ,  H05K1/02 ,  H05K1/18 ,  H01L21/48 ,  H01L25/065

CPC classification number: H01L23/49833 ,  H01L21/4857 ,  H01L23/15 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15788 ,  H05K1/0201 ,  H05K1/181 ,  H05K2201/068 ,  H01L2924/00

Abstract: Methods and apparatus are provide for an interposer for interconnecting one or more semiconductor chips with an organic substrate in a semiconductor package, the interposer including: a first glass substrate having first and second opposing major surfaces, the first glass substrate having a first coefficient of thermal expansion (CTE1); a second glass substrate having first and second opposing major surfaces, the second glass substrate having a second coefficient of thermal expansion (CTE2); and an interface disposed between the first and second glass substrates and joining the second major surface of the first glass substrate to the first major surface of the second glass substrate, where CTE1 is less than CTE2, the first major surface of the first glass substrate operates to engage the one or more semiconductor chips, and the second major surface of the second glass substrate operates to engage the organic substrate.

公开(公告)号：US20170025341A1

公开(公告)日：2017-01-26

申请号：US15287163

申请日：2016-10-06

Applicant: CORNING INCORPORATED

Inventor： Satish Chandra Chaparala ,  Scott Christopher Pollard

IPC: H01L23/498 ,  H01L21/48 ,  H01L25/065

CPC classification number: H01L23/49833 ,  H01L21/4857 ,  H01L23/15 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15788 ,  H05K1/0201 ,  H05K1/181 ,  H05K2201/068 ,  H01L2924/00

Abstract: Methods and apparatus are provide for an interposer for interconnecting one or more semiconductor chips with an organic substrate in a semiconductor package, the interposer including: a first glass substrate having first and second opposing major surfaces, the first glass substrate having a first coefficient of thermal expansion (CTE1); a second glass substrate having first and second opposing major surfaces, the second glass substrate having a second coefficient of thermal expansion (CTE2); and an interface disposed between the first and second glass substrates and joining the second major surface of the first glass substrate to the first major surface of the second glass substrate, where CTE1 is less than CTE2, the first major surface of the first glass substrate operates to engage the one or more semiconductor chips, and the second major surface of the second glass substrate operates to engage the organic substrate.

Abstract translation: 提供了用于将一个或多个半导体芯片与半导体封装中的有机衬底互连的插入件的方法和装置，所述插入器包括：具有第一和第二相对主表面的第一玻璃衬底，所述第一玻璃衬底具有第一热导率 扩展（CTE1）; 具有第一和第二相对主表面的第二玻璃基板，所述第二玻璃基板具有第二热膨胀系数（CTE2）; 以及设置在第一和第二玻璃基板之间并且将第一玻璃基板的第二主表面接合到第二玻璃基板的第一主表面的接口，其中CTE1小于CTE2，第一玻璃基板的第一主表面操作 以接合一个或多个半导体芯片，并且第二玻璃基板的第二主表面操作以接合有机基板。

公开(公告)号：US20200031710A1

公开(公告)日：2020-01-30

申请号：US16500997

申请日：2018-04-04

Applicant: CORNING INCORPORATED

Inventor： Satish Chandra Chaparala ,  Kristen Lorraine Eckart ,  Kurt Edward Gerber ,  Ming-Huang Huang ,  Nagaraja Shashidhar ,  Huan-Hung Sheng ,  Michael Lesley Sorensen ,  Ananthanarayanan Subramanian

IPC: C03C21/00 ,  C03C15/00 ,  C03C27/10 ,  B32B17/10 ,  B32B7/12 ,  B32B37/12 ,  B32B37/18 ,  H05K1/02

Abstract: A multi-layer and method of making the same are provided. The multi-layer, such as a sensor, can include a high strength glass overlay and a lamination layer on a substrate layer. The overlay can be less than 250 micrometers thick and have at least one tempered surface incorporating a surface compression layer of at least 5 micrometers deep and a surface compressive stress of at least 200 MPa. The overlay can exhibit a puncture factor of at least 3000 N/μm2 at B10 (10thpercentile of the probability distribution of failure) in a multi-layer structure, an apparent thickness of less than 0.014 mm, and a pencil hardness greater than 6H. The method can include ion-exchange tempering at least one major surface of a glass sheet, light etching the major surface to remove flaws and laminating the glass sheet on the tempered and lightly etched major surface to a substrate layer.

公开(公告)号：US10195825B2

公开(公告)日：2019-02-05

申请号：US15521662

申请日：2015-10-29

Applicant: Corning Incorporated

Inventor： Satish Chandra Chaparala

IPC: B32B3/00 ,  B32B17/06 ,  C03C15/00 ,  C03B17/02 ,  C03B23/203 ,  B24C1/04 ,  C03C3/085 ,  C03C3/087 ,  C03C3/091 ,  C03C3/093 ,  C03C8/02 ,  C03C19/00 ,  C03C23/00 ,  B32B3/02 ,  C03B17/06 ,  C03C13/00

Abstract: A method for strengthening an edge of a glass laminate including a glass core layer positioned between a first glass clad layer and a second glass clad layer may include forming a channel in the edge of the glass laminate. Sidewalls of the channel may be formed from the first glass clad layer and the second glass clad layer. Glass filler material having a filler coefficient of thermal expansion greater than a core coefficient of thermal expansion may be positioned in the channel. The glass filler material and the sidewalls of the channel may be fused to the second glass clad layer thereby forming an edge cap over the channel. The edge of the glass laminate is under compressive stress after the glass filler material is enclosed in the channel.

公开(公告)号：US20170246841A1

公开(公告)日：2017-08-31

申请号：US15521662

申请日：2015-10-29

Applicant: Corning Incorporated

Inventor： Satish Chandra Chaparala

IPC: B32B17/06 ,  C03B17/06 ,  C03B23/203 ,  C03C15/00 ,  C03C19/00 ,  B24C1/04 ,  C03C3/093 ,  C03C3/085 ,  C03C3/087 ,  C03C3/091 ,  C03C8/02 ,  C03C13/00 ,  B32B3/02 ,  C03C23/00

CPC classification number: B32B17/06 ,  B24C1/04 ,  B32B3/02 ,  B32B2250/03 ,  B32B2307/558 ,  B32B2419/00 ,  B32B2457/12 ,  B32B2457/208 ,  B32B2509/00 ,  B32B2605/00 ,  C03B17/02 ,  C03B17/064 ,  C03B23/203 ,  C03C3/085 ,  C03C3/087 ,  C03C3/091 ,  C03C3/093 ,  C03C8/02 ,  C03C13/00 ,  C03C15/00 ,  C03C19/00 ,  C03C23/0025 ,  C03C23/005 ,  C03C2207/00 ,  C03C2213/00

Abstract: A method for strengthening an edge of a glass laminate including a glass core layer positioned between a first glass clad layer and a second glass clad layer may include forming a channel in the edge of the glass laminate. Sidewalls of the channel may be formed from the first glass clad layer and the second glass clad layer. Glass filler material having a filler coefficient of thermal expansion greater than a core coefficient of thermal expansion may be positioned in the channel. The glass filler material and the sidewalls of the channel may be fused to the second glass clad layer thereby forming an edge cap over the channel. The edge of the glass laminate is under compressive stress after the glass filler material is enclosed in the channel.

公开(公告)号：US11591257B2

公开(公告)日：2023-02-28

申请号：US16500997

申请日：2018-04-04

Applicant: CORNING INCORPORATED

Inventor： Satish Chandra Chaparala ,  Kristen Lorraine Eckart ,  Kurt Edward Gerber ,  Ming-Huang Huang ,  Nagaraja Shashidhar ,  Huan-Hung Sheng ,  Michael Lesley Sorensen ,  Ananthanarayanan Subramanian

IPC: C03C21/00 ,  B32B17/10 ,  B32B37/12 ,  B32B37/18 ,  C03C15/00 ,  C03C27/10 ,  H05K1/02 ,  B32B7/12 ,  H05K5/00 ,  H05K5/03

Abstract: A multi-layer and method of making the same are provided. The multi-layer, such as a sensor, can include a high strength glass overlay and a lamination layer on a substrate layer. The overlay can be less than 250 micrometers thick and have at least one tempered surface incorporating a surface compression layer of at least 5 micrometers deep and a surface compressive stress of at least 200 MPa. The overlay can exhibit a puncture factor of at least 3000 N/μm2 at B10 (10th percentile of the probability distribution of failure) in a multi-layer structure, an apparent thickness of less than 0.014 mm, and a pencil hardness greater than 6H. The method can include ion-exchange tempering at least one major surface of a glass sheet, light etching the major surface to remove flaws and laminating the glass sheet on the tempered and lightly etched major surface to a substrate layer.

公开(公告)号：US20150221571A1

公开(公告)日：2015-08-06

申请号：US14608537

申请日：2015-01-29

Applicant: CORNING INCORPORATED

Inventor： Satish Chandra Chaparala ,  Scott Christopher Pollard

IPC: H01L23/15 ,  H05K1/18 ,  H05K1/02 ,  H01L23/00

CPC classification number: H01L23/49833 ,  H01L21/4857 ,  H01L23/15 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15788 ,  H05K1/0201 ,  H05K1/181 ,  H05K2201/068 ,  H01L2924/00

Abstract: Methods and apparatus are provide for an interposer for interconnecting one or more semiconductor chips with an organic substrate in a semiconductor package, the interposer including: a first glass substrate having first and second opposing major surfaces, the first glass substrate having a first coefficient of thermal expansion (CTE1); a second glass substrate having first and second opposing major surfaces, the second glass substrate having a second coefficient of thermal expansion (CTE2); and an interface disposed between the first and second glass substrates and joining the second major surface of the first glass substrate to the first major surface of the second glass substrate, where CTE1 is less than CTE2, the first major surface of the first glass substrate operates to engage the one or more semiconductor chips, and the second major surface of the second glass substrate operates to engage the organic substrate.

Abstract translation: 提供了用于将一个或多个半导体芯片与半导体封装中的有机衬底互连的插入件的方法和装置，所述插入器包括：具有第一和第二相对主表面的第一玻璃衬底，所述第一玻璃衬底具有第一热导率 扩展（CTE1）; 具有第一和第二相对主表面的第二玻璃基板，所述第二玻璃基板具有第二热膨胀系数（CTE2）; 以及设置在第一和第二玻璃基板之间并且将第一玻璃基板的第二主表面接合到第二玻璃基板的第一主表面的接口，其中CTE1小于CTE2，第一玻璃基板的第一主表面操作 以接合一个或多个半导体芯片，并且第二玻璃基板的第二主表面操作以接合有机基板。

公开(公告)号：US20150131949A1

公开(公告)日：2015-05-14

申请号：US14334839

申请日：2014-07-18

Applicant: Corning Incorporated

Inventor： Venkata Adiseshaiah Bhagavatula ,  Roy Joseph Bourcier ,  Satish Chandra Chaparala ,  John Himmelreich

IPC: G02B6/255

CPC classification number: G02B6/2551 ,  B29C65/1406 ,  B29C65/16 ,  B29C65/1616 ,  B29C65/1619 ,  B29C65/4815 ,  B29C65/4835 ,  B29C65/484 ,  B29C65/4845 ,  B29C65/72 ,  B29C66/21 ,  B29C66/3452 ,  B29C2035/0822 ,  B29C2035/0827 ,  G02B6/3801 ,  G02B6/4237 ,  G02B6/4239 ,  Y10T428/269 ,  Y10T428/31551 ,  Y10T428/31663 ,  Y10T428/31721

Abstract: A method of assembling optoelectronic and/or photonic components, said method comprising: (i) providing at least two optoelectronic and/or photonic components; (ii) aligning and situating these components relative to one another and in close proximity with one another so as to: (a) provide optical coupling between these components; and (b) maintain the distance d between the adjacent parts of these components, where d is 0 to 100 μm; (iii) adhering these components to one another with while maintaining optical coupling therebetween; and (iv) laser welding these components together while maintaining optical coupling therebetween.

Abstract translation: 一种组装光电子和/或光子组件的方法，所述方法包括：（i）提供至少两个光电子和/或光子分量; （ii）使这些部件相对于彼此并且彼此紧密地对准和定位，以便：（a）在这些部件之间提供光耦合; 和（b）保持这些组分的相邻部分之间的距离d，其中d为0至100μm; （iii）在保持它们之间的光耦合的同时将这些部件彼此粘合; 和（iv）将这些部件激光焊接在一起，同时保持它们之间的光耦合。