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1.发明授权公开(公告)号：US09377843B2
公开(公告)日：2016-06-28
申请号：US13907810
申请日：2013-05-31
Applicant: Broadcom Corporation
Inventor： Xicheng Jiang
CPC classification number: G06F1/324 , G06F1/06 , G06F1/08 , G06F1/3237 , Y02D10/126 , Y02D10/128 , Y02D50/20
Abstract: Systems and methods for managing current consumption by an electronic device are provided. The electronic device includes first and second clock units. The first clock unit generates a first reference clock signal based on a first current input. The second clock unit generates a second reference clock signal based on a second current input greater than the first current input. The system includes a control module configured to identify an application to be executed. The control module is configured to determine whether the application is associated with a first current consumption level or a second current consumption level greater than the first current consumption level. The control module is configured to select the first or second reference clock signal based on whether the application is determined to be associated with the first or second current consumption level. The system includes circuitry configured to execute the application based on the selection.
Abstract translation: 提供了一种用于管理电子设备的电流消耗的系统和方法。 电子设备包括第一和第二时钟单元。 第一时钟单元基于第一电流输入产生第一参考时钟信号。 第二时钟单元基于大于第一电流输入的第二电流输入产生第二参考时钟信号。 该系统包括被配置为识别要执行的应用的控制模块。 控制模块被配置为确定应用是否与大于第一当前消费水平的第一电流消耗水平或第二电流消耗水平相关联。 控制模块被配置为基于是否将应用确定为与第一或第二电流消耗水平相关联来选择第一或第二参考时钟信号。 该系统包括经配置以基于该选择来执行该应用的电路。
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公开(公告)号：US20150180430A1
公开(公告)日：2015-06-25
申请号：US14144262
申请日：2013-12-30
Applicant: Broadcom Corporation
Inventor： Zhengyu Wang , Iuri Mehr , Jungwoo Song , Xicheng Jiang
IPC: H03F3/217
CPC classification number: H03F3/2175 , H03F3/217 , H03F2200/351
Abstract: Methods, systems, and apparatuses for detecting and suppressing analog error in an output stage of a digital class-D amplifier are described. In embodiments, the digital class-D amplifier includes a PWM stage, an output stage, and a feedback circuit. The PWM stage receives the signal difference between an input digital signal and a feedback digital signal, generates a digital pulse-width modulated (PWM) signal based thereon, and provides the digital PWM signal as a first component of the digital feedback signal. The output stage receives the digital PWM signal and generates an analog output signal for driving a load responsive to the digital PWM signal. The feedback circuit combines an analog representation of the PWM signal and the analog output signal to generate a second component of the digital feedback signal.
Abstract translation: 描述了用于检测和抑制数字D类放大器的输出级中的模拟错误的方法，系统和装置。 在实施例中，数字D类放大器包括PWM级，输出级和反馈电路。 PWM级接收输入数字信号和反馈数字信号之间的信号差，基于此产生数字脉宽调制（PWM）信号，并提供数字PWM信号作为数字反馈信号的第一分量。 输出级接收数字PWM信号，并产生用于响应于数字PWM信号驱动负载的模拟输出信号。 反馈电路组合了PWM信号和模拟输出信号的模拟表示，以产生数字反馈信号的第二分量。
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公开(公告)号：US20150097627A1
公开(公告)日：2015-04-09
申请号：US14047306
申请日：2013-10-07
Applicant: Broadcom Corporation
Inventor： Xicheng Jiang
IPC: H03L7/06
Abstract: A clock generation system provides a low power approach for generating clock signals. The clock generation system may use a free running clock and, at intervals, maintain the accuracy of the free running clock. The free running clock may be the source of other system clocks, such as a 32 KHz clock for system timing and a 13 MHz clock to facilitate audio playback, e.g., MP3 decoding and playback. The clock generation system eliminates the need for two different crystal oscillators and a complex PLL for generating the low frequency clock.
Abstract translation: 时钟发生系统提供低功率方式来产生时钟信号。 时钟发生系统可以使用自由运行的时钟，并且间隔地保持自由运行时钟的精度。 自由运行的时钟可能是其他系统时钟的来源，例如用于系统定时的32KHz时钟和用于促进音频回放（例如MP3解码和回放）的13MHz时钟。 时钟发生系统不需要两个不同的晶体振荡器和用于产生低频时钟的复合PLL。
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公开(公告)号：US20150066438A1
公开(公告)日：2015-03-05
申请号：US14473635
申请日：2014-08-29
Applicant: BROADCOM CORPORATION
Inventor： Todd Lee Brooks , Xicheng Jiang , Iuri Mehr , David Joseph Stoops , Vinod Jayakumar , Min Gyu Kim , Hui Zheng , I-Ning Ku , Vinay Chandrasekhar , Yee Ling Cheung
IPC: H03B5/04 , G01R19/00 , G01K1/00 , G01L7/00 , A61B5/021 , H05B33/08 , A61B5/01 , A61B5/024 , A61B5/08 , G01J1/00 , G01N33/00
CPC classification number: H05B33/089 , A61B5/01 , A61B5/021 , A61B5/024 , A61B5/0816 , A61B2562/06 , G01J1/44 , G01K1/02 , G01R19/0092 , H03K3/0231
Abstract: A sensor interface includes on-chip relaxation oscillator circuit and a PLL that operate cooperatively to generate a highly accurate clock signal on-chip using low-power components. A photodiode generates a current signal based on an optical signal that is representative of a sensor signal. An ADC that operates based on the highly accurate clock signal generates a digital signal based on the current signal generated by the photodiode, and a processor processed the digital signal to estimate sensor data within the sensor signal. Examples of characteristics that may be sensed can include environmental characteristics (e.g., temperature, humidity, barometric pressure, etc.) and/or biomedical characteristics (e.g., body temperature, heart rate, respiratory rate, blood pressure, etc.). In desired, an amplifier processes the photodiode-provided current signal before it is provided to the ADC. Also, one or more CDACs that generate feedback currents may be used to reduce noise sensitivity of the sensor interface.
Abstract translation: 传感器接口包括片上弛豫振荡器电路和PLL，其协作地工作以使用低功率元件在片上产生高精度的时钟信号。 光电二极管基于表示传感器信号的光信号产生电流信号。 基于高度精确的时钟信号操作的ADC基于由光电二极管产生的电流信号产生数字信号，并且处理器处理数字信号以估计传感器信号内的传感器数据。 可以感测的特征的实例可以包括环境特征（例如，温度，湿度，大气压力等）和/或生物医学特征（例如体温，心率，呼吸频率，血压等）。 在期望的情况下，放大器在将其提供给ADC之前处理提供的光电二极管的电流信号。 而且，可以使用产生反馈电流的一个或多个CDAC来降低传感器接口的噪声灵敏度。
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公开(公告)号：US09276587B2
公开(公告)日：2016-03-01
申请号：US14047306
申请日：2013-10-07
Applicant: Broadcom Corporation
Inventor： Xicheng Jiang
Abstract: A clock generation system provides a low power approach for generating clock signals. The clock generation system may use a free running clock and, at intervals, maintain the accuracy of the free running clock. The free running clock may be the source of other system clocks, such as a 32 KHz clock for system timing and a 13 MHz clock to facilitate audio playback, e.g., MP3 decoding and playback. The clock generation system eliminates the need for two different crystal oscillators and a complex PLL for generating the low frequency clock.
Abstract translation: 时钟发生系统提供低功率方式来产生时钟信号。 时钟发生系统可以使用自由运行的时钟，并且间隔地保持自由运行时钟的精度。 自由运行的时钟可能是其他系统时钟的来源，例如用于系统定时的32KHz时钟和用于促进音频回放（例如MP3解码和回放）的13MHz时钟。 时钟发生系统不需要两个不同的晶体振荡器和用于产生低频时钟的复合PLL。
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Patent Agency Ranking
公开(公告)号：US09756699B2
公开(公告)日：2017-09-05
申请号：US14473635
申请日：2014-08-29
Applicant: BROADCOM CORPORATION
Inventor： Todd Lee Brooks , Xicheng Jiang , Iuri Mehr , David Joseph Stoops , Vinod Jayakumar , Min Gyu Kim , Hui Zheng , I-Ning Ku , Vinay Chandrasekhar , Yee Ling Cheung
IPC: H04B15/00 , H05B33/08 , G01R19/00 , H03K3/0231 , G01K1/02 , A61B5/01 , A61B5/024 , A61B5/08 , A61B5/021 , G01J1/44
CPC classification number: H05B33/089 , A61B5/01 , A61B5/021 , A61B5/024 , A61B5/0816 , A61B2562/06 , G01J1/44 , G01K1/02 , G01R19/0092 , H03K3/0231
Abstract: A sensor interface includes on-chip relaxation oscillator circuit and a PLL that operate cooperatively to generate a highly accurate clock signal on-chip using low-power components. A photodiode generates a current signal based on an optical signal that is representative of a sensor signal. An ADC that operates based on the highly accurate clock signal generates a digital signal based on the current signal generated by the photodiode, and a processor processed the digital signal to estimate sensor data within the sensor signal. Examples of characteristics that may be sensed can include environmental characteristics (e.g., temperature, humidity, barometric pressure, etc.) and/or biomedical characteristics (e.g., body temperature, heart rate, respiratory rate, blood pressure, etc.). If desired, an amplifier processes the photodiode-provided current signal before it is provided to the ADC. Also, one or more CDACs that generate feedback currents may be used to reduce noise sensitivity of the sensor interface.
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公开(公告)号：US09564794B2
公开(公告)日：2017-02-07
申请号：US14139257
申请日：2013-12-23
Applicant: Broadcom Corporation
Inventor： I-Ning Ku , Hui Zheng , Jungwoo Song , Xicheng Jiang
CPC classification number: H02M1/14 , H02M3/07 , H02M2003/077
Abstract: Systems, apparatuses, and methods provided for ping-pong charge pumps. Flying capacitors present in ping-pong charge pumps are operated out of phase to increase equalization periods. Out-of-phase operation also decreases voltage differences between flying capacitors during equalization periods thus decreasing ping-pong charge pump output voltage ripple and snapback. The voltages of the flying capacitors may be equalized without the use of an equalization switch. Differential control currents that are based on the voltage difference between the flying capacitors are used to enable or disable the flying capacitors from driving an output load of the ping-pong charge pump during certain phases of operation. A capacitor with a lower voltage may be disabled, thus providing for voltage equalization as the enabled capacitor sources current to the output load. The flying capacitors are also equalized during overlapping time periods in which the flying capacitors are charging.
Abstract translation: 为乒乓电荷泵提供的系统，设备和方法。 乒乓电荷泵中存在的飞电容器异相运行，以增加均衡周期。 异相操作也会在均衡期间降低飞溅电容器之间的电压差，从而减少乒乓电荷泵输出电压纹波和回跳。 可以在不使用均衡开关的情况下使飞行电容器的电压相等。 基于飞跨电容器之间的电压差的差分控制电流用于在某些操作阶段启用或禁用飞镖电容器驱动乒乓电荷泵的输出负载。 可以禁用具有较低电压的电容器，从而在使能电容器电流流向输出负载时提供电压均衡。 飞行电容器在飞行电容器充电的重叠时间段期间也相等。
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公开(公告)号：US20140266099A1
公开(公告)日：2014-09-18
申请号：US13843202
申请日：2013-03-15
Applicant: BROADCOM CORPORATION
Inventor： I-Ning Ku , Hui Zheng , Xicheng Jiang
IPC: G05F1/46
Abstract: A circuit for a charge-pump low-dropout (LDO) regulator may include a comparator circuit configured to control a pass transistor based on an error signal. A pre-charge path may be provided between a supply voltage and an output node of the regulator. The pre-charge path may be configured to allow charging of an output capacitor to a pre-charge voltage during a pre-charge operation mode. The output capacitor may be coupled between the output node of the regulator and ground potential. The pass transistor may be configured to allow charging of the output capacitor during an LDO mode of operation. A charge-pump circuit may be configured to provide a current for charging the output capacitor during the LDO mode of operation.
Abstract translation: 用于电荷泵低压差（LDO）调节器的电路可以包括被配置为基于误差信号来控制传输晶体管的比较器电路。 可以在调节器的电源电压和输出节点之间提供预充电路径。 预充电路径可以被配置为允许在预充电操作模式期间将输出电容器充电到预充电电压。 输出电容器可以耦合在调节器的输出节点和地电位之间。 传输晶体管可以被配置为允许在LDO操作模式期间对输出电容器进行充电。 电荷泵电路可以被配置为在LDO操作模式期间提供用于对输出电容器充电的电流。
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公开(公告)号：US08798219B2
公开(公告)日：2014-08-05
申请号：US13768923
申请日：2013-02-15
Applicant: Broadcom Corporation
Inventor： Aaron W. Buchwald , Michael Le , Josephus van Engelen , Xicheng Jiang , Hui Wang , Howard A. Baumer , Avanindra Madisetti
IPC: H04L7/02
CPC classification number: H04L25/03885 , H03L7/07 , H03L7/0814 , H03L7/091 , H04L7/0025 , H04L7/0274 , H04L7/0337 , H04L25/03006 , H04L2025/03477 , H04L2025/03617
Abstract: A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.
Abstract translation: 高速串行数据收发器包括多个接收器和发送器，用于以千兆比特每秒的数据速率接收和发送多个模拟串行数据信号。 每个接收机包括用于跟踪与接收机相关联的串行数据信号的相位和频率的定时恢复系统。 定时恢复系统包括响应于相位控制信号的相位内插器和具有不同预定相位的一组参考信号。 相位内插器导出具有内插相位的采样信号以采样串行数据信号。 每个接收机中的定时恢复系统独立地对采样信号和与接收机相关联的串行数据信号进行频率同步。 接收机可以包括多个路径，用于根据多个具有内插相位的多个时间交错采样信号对接收的串行数据信号进行采样。
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10.发明授权Analog and audio mixed-signal front end for 4G/LTE cellular system-on-chip 有权用于4G / LTE蜂窝系统芯片的模拟和音频混合信号前端公开(公告)号：US09413375B2
公开(公告)日：2016-08-09
申请号：US14586866
申请日：2014-12-30
Applicant: Broadcom Corporation
Inventor： Xicheng Jiang , Xinyu Yu , Fang Lin , Yee Ling Cheung , Michael Inerfield
CPC classification number: H03M1/185 , H03M1/66 , H04B1/0003 , H04B1/1646 , H04B1/40 , H04M1/0202
Abstract: A CMOS analog and audio front-end circuit includes an enhanced analog-to-digital converter (ADC) that achieves a desired signal-to-noise-and-distortion (SNDR) and an analog-front-end transmit (TX) digital-to-analog converter (DAC). The enhanced ADC includes an improved single Op-Amp resonator coupled to a feed-forward loop and can substantially reduce signal transfer function (STF) peaking of the enhanced ADC. The CMOS analog and audio front-end circuit is integrated with a baseband processor.
Abstract translation: CMOS模拟和音频前端电路包括增强的模数转换器（ADC），其实现期望的信噪比失真（SNDR）和模拟前端发送（TX）数字 - 模数转换器（DAC）。 增强型ADC包括耦合到前馈环路的改进的单个运算放大器，可以显着降低增强型ADC的信号传递函数（STF）峰值。 CMOS模拟和音频前端电路与基带处理器集成在一起。
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