Abstract:
Methods, systems, and apparatuses for detecting and suppressing analog error in an output stage of a digital class-D amplifier are described. In embodiments, the digital class-D amplifier includes a PWM stage, an output stage, and a feedback circuit. The PWM stage receives the signal difference between an input digital signal and a feedback digital signal, generates a digital pulse-width modulated (PWM) signal based thereon, and provides the digital PWM signal as a first component of the digital feedback signal. The output stage receives the digital PWM signal and generates an analog output signal for driving a load responsive to the digital PWM signal. The feedback circuit combines an analog representation of the PWM signal and the analog output signal to generate a second component of the digital feedback signal.
Abstract:
Systems, apparatuses, and methods provided for ping-pong charge pumps. Flying capacitors present in ping-pong charge pumps are operated out of phase to increase equalization periods. Out-of-phase operation also decreases voltage differences between flying capacitors during equalization periods thus decreasing ping-pong charge pump output voltage ripple and snapback. The voltages of the flying capacitors may be equalized without the use of an equalization switch. Differential control currents that are based on the voltage difference between the flying capacitors are used to enable or disable the flying capacitors from driving an output load of the ping-pong charge pump during certain phases of operation. A capacitor with a lower voltage may be disabled, thus providing for voltage equalization as the enabled capacitor sources current to the output load. The flying capacitors are also equalized during overlapping time periods in which the flying capacitors are charging.
Abstract:
Methods, systems, and apparatuses for detecting and suppressing analog error in an output stage of a digital class-D amplifier are described. In embodiments, the digital class-D amplifier includes a PWM stage, an output stage, and a feedback circuit. The PWM stage receives the signal difference between an input digital signal and a feedback digital signal, generates a digital pulse-width modulated (PWM) signal based thereon, and provides the digital PWM signal as a first component of the digital feedback signal. The output stage receives the digital PWM signal and generates an analog output signal for driving a load responsive to the digital PWM signal. The feedback circuit combines an analog representation of the PWM signal and the analog output signal to generate a second component of the digital feedback signal.
Abstract:
Systems, apparatuses, and methods provided for ping-pong charge pumps. Flying capacitors present in ping-pong charge pumps are operated out of phase to increase equalization periods. Out-of-phase operation also decreases voltage differences between flying capacitors during equalization periods thus decreasing ping-pong charge pump output voltage ripple and snapback. The voltages of the flying capacitors may be equalized without the use of an equalization switch. Differential control currents that are based on the voltage difference between the flying capacitors are used to enable or disable the flying capacitors from driving an output load of the ping-pong charge pump during certain phases of operation. A capacitor with a lower voltage may be disabled, thus providing for voltage equalization as the enabled capacitor sources current to the output load. The flying capacitors are also equalized during overlapping time periods in which the flying capacitors are charging.
Abstract:
A multi-mode line driver circuit designed to be fabricated in a CMOS process and capable of supporting a plurality of operating modes corresponding, for example, to different profiles of communication standards such as xDSL standards. The line driver circuit incorporates integrated mode switches with a two-stage amplifier architecture to relax amplifier requirements by distributing the signal gain into two amplifier stages. Reconfigurable feedback loops are provided to permit design optimization for particular modes of operation (e.g., ADSL and VDSL compliant modes). In one embodiment implemented as a Class-H amplifier, lift amplifier(s) are provided between a first amplifier stage and a second amplifier stage for controlling voltage supply levels of the second amplifier stage. The lift amplifiers may be enabled by voltage threshold detection circuitry that monitors either the input or the output signals of the first amplifier stage depending on the operable transmission mode.
Abstract:
A multi-mode line driver circuit designed to be fabricated in a CMOS process and capable of supporting a plurality of operating modes corresponding, for example, to different profiles of communication standards such as xDSL standards. The line driver circuit incorporates integrated mode switches with a two-stage amplifier architecture to relax amplifier requirements by distributing the signal gain into two amplifier stages. Reconfigurable feedback loops are provided to permit design optimization for particular modes of operation (e.g., ADSL and VDSL compliant modes). In one embodiment implemented as a Class-H amplifier, lift amplifier(s) are provided between a first amplifier stage and a second amplifier stage for controlling voltage supply levels of the second amplifier stage. The lift amplifiers may be enabled by voltage threshold detection circuitry that monitors either the input or the output signals of the first amplifier stage depending on the operable transmission mode.