Abstract:
The present disclosure provides an array substrate, a manufacturing method thereof and a display device. The array substrate includes: a display area and a peripheral area surrounding the display area; the display area is provided with a plurality of gate lines and a plurality of data lines, the gate lines and the data lines are crossed to define a plurality of sub-pixel regions distributed in an array; a first electrode, the first electrode including a first portion located in the display area and a second portion located in the peripheral area; an electrode connection line, the electrode connection line is located in the peripheral area, the electrode connection line is electrically connected to the second portion; a plurality of compensation signal lines, at least part of the compensation signal lines are located in the display area, and the compensation signal lines are electrically connected to the first portion.
Abstract:
The present disclosure provides a shift register, a gate driving circuit, a display panel, and a driving method thereof. The shift register includes: an input circuit; an output circuit; a first control circuit configured to provide a potential of a first control signal terminal to a pull-down node, and provide a potential of a reference signal terminal to the pull-down node according to the potential of the pull-up node; and a second control circuit connected to the pull-down node, a second control signal terminal, the output signal terminal, and the reference signal terminal, wherein the second control circuit is configured to pull down a potential of the output signal terminal during a display phase under the control of a potential of the pull-down node and a potential of the second control signal terminal, and pull up the potential of the output signal terminal in a power-off phase.
Abstract:
Provided are a display panel, a preparation method thereof, and a display apparatus. The display panel includes a first substrate and a second substrate disposed oppositely, and a liquid crystal layer sandwiched between the first substrate and the second substrate, wherein the first substrate includes a black matrix layer and a color filter layer which are sequentially disposed on a first base substrate; at least one of the first substrate and the second substrate further includes a spacer; and the black matrix layer includes at least one first black matrix, and an orthographic projection of each first black matrix on the first base substrate covers an orthographic projection of the spacer on the first base substrate.
Abstract:
A liquid crystal display panel and a display device. The liquid crystal display panel includes a display region and an opening region in the display region; the display region includes a plurality of sub-pixels, the display region includes a first edge and a second edge opposite to the first edge, the display region includes a first region between the opening region and the first edge and a second region between the opening region and the second edge, an orthographic projection of the opening region on the first edge respectively coincides with orthographic projections of the first region and the second region on the first edge, the plurality of sub-pixels comprise a main sub-pixel in the first region and a secondary sub-pixel in the second region, and an area of the main sub-pixel is smaller than an area of the secondary sub-pixel.
Abstract:
The present disclosure provides a display device comprising a display panel, wherein a first polarizer is arranged at a side of the display panel that is opposite to the side for displaying images, and a functional component with a grid structure and a second polarizer are arranged in sequence along the direction away from the display panel at the side for displaying images, the second polarizer being capable of scattering light rays that penetrate the second polarizer.
Abstract:
There are disclosed a liquid crystal panel and method for the manufacture thereof, and a 3D display apparatus, for enabling left-eye and right-eye images to be separated directly by means of a liquid crystal cell and the manufacturing process of a naked-eye 3D mode liquid crystal cell to be simplified. The liquid crystal panel comprises an upper substrate, a lower substrate and a liquid crystal cell formed of liquid crystal molecules located between the upper and lower substrates. The liquid crystal cell comprises a display layer and a grating layer, the grating layer being arranged in proximity to the upper substrate, the grating layer comprising a light shielding region and a light transmitting region, the light shielding region comprising light shielding liquid crystal molecules, the light transmitting region comprising light transmitting liquid crystal molecules, the light shielding region and the light transmitting region being arranged alternately. The present disclosure provides a liquid crystal panel that is capable of separating left-eye and right-eye images directly by means of a liquid crystal cell and simplifying the manufacturing process of a naked-eye 3D mode liquid crystal cell.
Abstract:
The present disclosure provides a driving module and a display device. The driving module includes a serial-parallel conversion circuit and a data providing circuit, the serial-parallel conversion circuit is configured to convert a serial input signal into a parallel output signal and generate a transmission control signal and a common electrode voltage signal in accordance with mode indication information carried by the parallel output signal, and the parallel output signal carries the mode indication information and input display data; and the data providing circuit is configured to convert the input display data into output display data and transmit the output display data to a corresponding data line under the control of the transmission control signal. According to the embodiments of the present disclosure, it is able to achieve display through relying on serial input signals and other signals provided by a system without a display chip.
Abstract:
A display substrate and a display apparatus are provided. The display substrate includes a base substrate; sub-pixels arranged in an array and on the base substrate; data line groups on the base substrate; each data line group includes data lines, each of which is connected to one column of sub-pixels; data selectors on the base substrate and connected to the data line groups in a one-to-one correspondence; data lines in a same data line group are connected to a same data selector; and data selection signal lines, wherein different data selection signal lines output different data selection signals; and different data lines connected to a same data selector correspond to different data selection signal lines, respectively. The display panel provided may effectively reduce the resistance on the data selection signal lines, thereby reducing the delay of the data selection signals and further improving the charging uniformity of sub-pixels.
Abstract:
A display substrate includes a display area, which includes a plurality of sub-areas arranged in a first direction. In at least one sub-area, the display substrate further includes a base substrate, a plurality of sub-pixels arranged in a fourth direction, a data line, and a first touch line extending in the fourth direction. The of sub-pixels include a first sub-pixel and a second sub-pixel, at least one first sub-pixel extends in a second direction, and at least one second sub-pixel extends in a third direction; The first, second, third and fourth directions intersect with one another. The data line is electrically connected to the sub-pixels through a plurality of input transistors. At least one input transistor includes a first electrode electrically connected to the sub-pixel. Orthographic projections of the first touch line and the first electrode on the base substrate do not overlap with each other.
Abstract:
A display panel includes: a base substrate including a display region and a fan-out region, and the fan-out region is located between the display region and a chip; a plurality of data wires/touch wires located in the fan-out region for respectively electrically connecting a plurality of data lines/touch signal lines with the chip. A portion of the plurality of data wires is located in a first conductive layer while a rest portion thereof is located in the second conductive layer. A portion of the plurality of touch wires is located in at least one of the first conductive layer and the second conductive layer while a rest portion thereof is located in the third conductive layer. A pitch between any two adjacent wires in the first/second/third conductive layer is a first/second/third wire pitch, respectively. The first wire pitch and the second wire pitch are smaller than the third wire pitch.