-
1.发明授权公开(公告)号：US10989947B2
公开(公告)日：2021-04-27
申请号：US16328562
申请日：2018-05-23
Inventor： Yun Qiao , Zhen Wang , Fei Huang , Xiaozhou Zhan , Han Zhang , Wenwen Qin , Jian Sun
IPC: G02F1/1333 , G02F1/1362 , G06F3/041
Abstract: Disclosed are an array substrate, a liquid crystal display panel and a display apparatus. The array substrate comprises a plurality of pixel units, with each of which being provided with a plurality of sub-pixels (R, G, B) arranged in a first direction; a plurality of touch control electrodes, a region where each of the touch control electrodes is located overlapping with a region where the plurality of sub-pixels (R, G, B) are located; and a plurality of touch control signal lines arranged in gaps between the sub-pixels (R, G, B), wherein each of the touch control signal lines is connected to each of the touch control electrodes, there is no touch control floating signal line not connected to each of the touch control electrodes, and one column of pixel units is correspondingly provided with one touch control signal line.
-
公开(公告)号：US10936139B2
公开(公告)日：2021-03-02
申请号：US16435082
申请日：2019-06-07
Inventor： Zhen Wang , Xiaozhou Zhan , Lele Cong , Yun Qiao , Jian Sun , Han Zhang , Wenwen Qin , Zhengkui Wang
Abstract: A touch panel including a substrate, an insulating layer, touch electrode blocks, and electrode lines. The touch electrode blocks include an array of first type touch electrode blocks having a regular shape and a second type touch electrode block having an irregular shape. Ones of the first type touch electrode blocks are electrically connected to respective ones of the electrode lines by respective X first contact vias extending through the insulating layer, and the respective X first contact vias are arranged along a straight line in a column direction. The second type touch electrode block is electrically connected to a first corresponding one of the electrode lines by Y second contact vias extending through the insulating layer, and the Y second contact vias are arranged along at least one straight line in the column direction. X and Y are natural numbers, and 0.75×X≤Y≤1.25×X.
-
公开(公告)号：US10714510B2
公开(公告)日：2020-07-14
申请号：US16201771
申请日：2018-11-27
Inventor： Lele Cong , Jian Sun , Zhengkui Wang , Wenwen Qin , Jianjun Zhang
IPC: H01L27/12
Abstract: An array substrate includes: a base substrate; at least one first connection terminal, at least one second connection terminal, and at least one connection line, which are disposed on the base substrate and located in a non-display area of the array substrate, the at least one connection line being connected with the at least one first connection terminal and the at least one second connection terminal; at least one gate line disposed on the base substrate and located in a display area of the array substrate. The first connection terminal is for connecting with an IC, and the second connection terminal is for connecting with a flexible circuit board. A resistivity of at least a part of each of at least one of the at least one connection line is less than a resistivity of the at least one gate line.
-
公开(公告)号：US20190287445A1
公开(公告)日：2019-09-19
申请号：US16059755
申请日：2018-08-09
Inventor： Yun Qiao , Zhen Wang , Zhengkui Wang , Han Zhang , Jian Sun , Xiaozhou Zhan , Fei Huang , Wenwen Qin , Jianjun Zhang
Abstract: An array substrate and a display panel are provided. The array substrate includes a base substrate having a notch, the base substrate comprising a first region and a second region on opposite sides of the notch; a plurality of gate lines disposed on the base substrate and configured to respectively drive a plurality of rows of pixels on the base substrate, each of the plurality of gate lines being interrupted by the notch into a first gate sub-line in the first region and a second gate sub-line in the second region; and a gate driving device in the first region and/or the second region, the gate driving device is configured such that the first gate sub-line and the second gate sub-line of each of the plurality of gate lines are simultaneously scanned.
-
公开(公告)号：US20190073932A1
公开(公告)日：2019-03-07
申请号：US15762337
申请日：2017-10-12
Inventor： Fei Huang , Jian Sun , Zhen Wang , Wenwen Qin , Xiaozhou Zhan
Abstract: A shift register unit includes an input circuit, an output circuit, a pull-down control circuit, and a pull-down circuit. The pull-down control circuit is coupled to a first power supply signal terminal, a second power supply signal terminal, a pull-up node, a pull-down node, and a reset signal terminal. The pull-down control circuit is configured to transmit a first power supply signal from the first power supply signal terminal to the pull-down node under a control of the first power supply signal, transmit the first power supply signal from the first power supply signal terminal to the pull-down node under a control of the reset signal, and transmit a second power supply signal from the second power supply signal terminal to the pull-down node under a control of the pull-up node.
-
Patent Agency Ranking
公开(公告)号：US12140999B2
公开(公告)日：2024-11-12
申请号：US17925658
申请日：2021-12-20
Applicant: BOE Technology Group Co., Ltd.
Inventor： Deshuai Wang , Jian Sun , Zhen Wang , Yue Shan , Wei Yan , Jian Zhang , Han Zhang , Wenwen Qin , Yadong Zhang , Xiaoyan Yang , Keyan Liu , Hong Liu
IPC: G06F1/16
Abstract: A display panel includes: a base substrate including a display region and a fan-out region, and the fan-out region is located between the display region and a chip; a plurality of data wires/touch wires located in the fan-out region for respectively electrically connecting a plurality of data lines/touch signal lines with the chip. A portion of the plurality of data wires is located in a first conductive layer while a rest portion thereof is located in the second conductive layer. A portion of the plurality of touch wires is located in at least one of the first conductive layer and the second conductive layer while a rest portion thereof is located in the third conductive layer. A pitch between any two adjacent wires in the first/second/third conductive layer is a first/second/third wire pitch, respectively. The first wire pitch and the second wire pitch are smaller than the third wire pitch.
-
公开(公告)号：US11961442B2
公开(公告)日：2024-04-16
申请号：US18032512
申请日：2020-10-21
Applicant: BOE Technology Group Co., Ltd.
Inventor： Wei Yan , Wenwen Qin , Yue Shan , Deshuai Wang , Jiguo Wang , Zhen Wang , Xiaoyan Yang , Han Zhang , Jian Zhang , Yadong Zhang , Jian Sun
CPC classification number: G09G3/20 , G11C19/28 , G09G2310/0286
Abstract: A shift register unit, a driving method, a drive circuit, and a display apparatus are disclosed. The shift register unit includes: a control circuit, which is configured to adjust signals of a first node and a second node according to an input signal end, a first control signal end, a second control signal end and a first reference signal end; a cascade circuit, which is configured to provide, according to the signal of the first node, a signal of a first cascade clock signal end to a cascade output end; and an output circuit, which is configured to provide, according to the signal of the first node, a signal of a control clock signal end to a drive output end, and provide, according to the signal of the second node, a signal of a second reference signal end to the drive output end.
-
公开(公告)号：US11630534B2
公开(公告)日：2023-04-18
申请号：US16476621
申请日：2019-01-10
Inventor： Yun Qiao , Zhen Wang , Xiaozhou Zhan , Han Zhang , Wenwen Qin , Peng Liu , Zhengkui Wang
Abstract: A wiring structure includes a plurality of first connection lines disposed in a first wiring layer and extending respectively from first ones of the plurality of first electrical contacts to first ones of the plurality of second electrical contacts, the first connection lines not intersecting each other; and a plurality of second connection lines disposed in a second wiring layer and extending respectively from second ones of the plurality of first electrical contacts to second ones of the plurality of second electrical contacts, the second connection lines not intersecting each other. An orthographic projection of any one of the first connection lines onto a plane parallel to the first and second wiring layers does not intersect an orthographic projection of any one of the second connection lines onto the plane.
-
公开(公告)号：US11488512B2
公开(公告)日：2022-11-01
申请号：US16714385
申请日：2019-12-13
Inventor： Zhen Wang , Han Zhang , Zhengkui Wang , Wei Yan , Yun Qiao , Wenwen Qin , Xiaozhou Zhan , Jian Sun , Jian Zhang , Deshuai Wang
IPC: G09G3/20
Abstract: A display panel, a display device and a display control method thereof are provided in the present disclosure. The display panel includes: a time division multiplexing multiplexer (MUX) signal input circuit, which is connected with each of the plurality of signal lines, and configured to input data signals of each frame of display image to the plurality of signal lines, and for each frame of display image, input trigger signals corresponding to sub-pixel units of different colors to the plurality of signal lines in a time-sharing manner; among the plurality of signal lines, electrical signals on a plurality of adjacent first signal lines are arranged in sequence according to an order of positive, positive, negative and negative; among the plurality of signal lines, a first signal line has a spacing distance from adjacent signal lines less than a preset value.
-
公开(公告)号：US10692460B2
公开(公告)日：2020-06-23
申请号：US16320070
申请日：2018-03-08
Inventor： Lele Cong , Jian Sun , Wenwen Qin , Han Zhang
Abstract: Embodiments of the present application provide a display driving circuit, a method for controlling the same, and a display apparatus. The display driving circuit includes a plurality of function multiplexing circuits, and each of the plurality of function multiplexing circuits includes a data transmission terminal, an enabling signal terminal, a first signal terminal and a second signal terminal, and is configured to provide a test signal to the data transmission terminal and release static electricity at the data transmission terminal through the first signal terminal or the second signal terminal under control of the enabling signal terminal, the first signal terminal, and the second signal terminal, wherein the data transmission terminal is configured to be connected to at least one data line.
-
-
-
-
-
-
-
-
-
Search Results
32
records
(took 0.016 seconds)
