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公开(公告)号：US12140999B2
公开(公告)日：2024-11-12
申请号：US17925658
申请日：2021-12-20
Applicant: BOE Technology Group Co., Ltd.
Inventor： Deshuai Wang , Jian Sun , Zhen Wang , Yue Shan , Wei Yan , Jian Zhang , Han Zhang , Wenwen Qin , Yadong Zhang , Xiaoyan Yang , Keyan Liu , Hong Liu
IPC: G06F1/16
Abstract: A display panel includes: a base substrate including a display region and a fan-out region, and the fan-out region is located between the display region and a chip; a plurality of data wires/touch wires located in the fan-out region for respectively electrically connecting a plurality of data lines/touch signal lines with the chip. A portion of the plurality of data wires is located in a first conductive layer while a rest portion thereof is located in the second conductive layer. A portion of the plurality of touch wires is located in at least one of the first conductive layer and the second conductive layer while a rest portion thereof is located in the third conductive layer. A pitch between any two adjacent wires in the first/second/third conductive layer is a first/second/third wire pitch, respectively. The first wire pitch and the second wire pitch are smaller than the third wire pitch.
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公开(公告)号：US11961442B2
公开(公告)日：2024-04-16
申请号：US18032512
申请日：2020-10-21
Applicant: BOE Technology Group Co., Ltd.
Inventor： Wei Yan , Wenwen Qin , Yue Shan , Deshuai Wang , Jiguo Wang , Zhen Wang , Xiaoyan Yang , Han Zhang , Jian Zhang , Yadong Zhang , Jian Sun
CPC classification number: G09G3/20 , G11C19/28 , G09G2310/0286
Abstract: A shift register unit, a driving method, a drive circuit, and a display apparatus are disclosed. The shift register unit includes: a control circuit, which is configured to adjust signals of a first node and a second node according to an input signal end, a first control signal end, a second control signal end and a first reference signal end; a cascade circuit, which is configured to provide, according to the signal of the first node, a signal of a first cascade clock signal end to a cascade output end; and an output circuit, which is configured to provide, according to the signal of the first node, a signal of a control clock signal end to a drive output end, and provide, according to the signal of the second node, a signal of a second reference signal end to the drive output end.
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公开(公告)号：US11630534B2
公开(公告)日：2023-04-18
申请号：US16476621
申请日：2019-01-10
Inventor： Yun Qiao , Zhen Wang , Xiaozhou Zhan , Han Zhang , Wenwen Qin , Peng Liu , Zhengkui Wang
Abstract: A wiring structure includes a plurality of first connection lines disposed in a first wiring layer and extending respectively from first ones of the plurality of first electrical contacts to first ones of the plurality of second electrical contacts, the first connection lines not intersecting each other; and a plurality of second connection lines disposed in a second wiring layer and extending respectively from second ones of the plurality of first electrical contacts to second ones of the plurality of second electrical contacts, the second connection lines not intersecting each other. An orthographic projection of any one of the first connection lines onto a plane parallel to the first and second wiring layers does not intersect an orthographic projection of any one of the second connection lines onto the plane.
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公开(公告)号：US11488512B2
公开(公告)日：2022-11-01
申请号：US16714385
申请日：2019-12-13
Inventor： Zhen Wang , Han Zhang , Zhengkui Wang , Wei Yan , Yun Qiao , Wenwen Qin , Xiaozhou Zhan , Jian Sun , Jian Zhang , Deshuai Wang
IPC: G09G3/20
Abstract: A display panel, a display device and a display control method thereof are provided in the present disclosure. The display panel includes: a time division multiplexing multiplexer (MUX) signal input circuit, which is connected with each of the plurality of signal lines, and configured to input data signals of each frame of display image to the plurality of signal lines, and for each frame of display image, input trigger signals corresponding to sub-pixel units of different colors to the plurality of signal lines in a time-sharing manner; among the plurality of signal lines, electrical signals on a plurality of adjacent first signal lines are arranged in sequence according to an order of positive, positive, negative and negative; among the plurality of signal lines, a first signal line has a spacing distance from adjacent signal lines less than a preset value.
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公开(公告)号：US10996529B2
公开(公告)日：2021-05-04
申请号：US16634701
申请日：2018-12-12
IPC: G02F1/1362 , G02F1/1345 , G02F1/1368 , G09G3/36
Abstract: An array substrate includes plural sub-pixels in plural rows and plural columns; plural data ports; Ndl data lines, each of the Ndl data lines connecting to a column of sub-pixels, the Ndl data lines being divided into plural groups, each group including N data lines; and a multiplexer including M control lines and plural switching units in one-to-one correspondence with the Ndl data lines, each control line being connected to and controlling Ndl M switching units. All of the N data lines in each group are connected to one data port through N switching units, respectively, the data lines in different groups are connected to different data ports, the N switching units corresponding to each group are controlled by N different control lines, respectively, and at least two of the N data lines in each group are provided with a data line another group therebetween.
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Patent Agency Ranking
公开(公告)号：US10930360B2
公开(公告)日：2021-02-23
申请号：US16242472
申请日：2019-01-08
Inventor： Peng Liu , Jun Fan , Yusheng Liu , Bailing Liu , Han Zhang , Zhen Wang , Yun Qiao , Zhengkui Wang , Lele Cong , Mei Li
Abstract: A shift register includes a first input sub-circuit configured to transfer a first input signal at a first input terminal to a first node in response to a first scan signal at a first scan terminal being active, a first level control sub-circuit configured to transfer a first power supply voltage at a first power supply terminal to a first output control node and a second output control node in response to the first node being at an active potential, and an output sub-circuit configured to transfer a first clock signal at a first clock terminal to a first output in response to the first output control node being at an active potential, and to transfer a second clock signal at a second clock terminal to a second output terminal in response to the second output control node being at an active potential.
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公开(公告)号：US10825537B2
公开(公告)日：2020-11-03
申请号：US16477362
申请日：2018-08-23
Inventor： Yishan Fu , Jun Fan , Fuqiang Li , Han Zhang
Abstract: A shift register unit, a driving method, a gate driving circuit and a display device are provided. The shift register unit includes: an input circuit used to provide a pull-up node with a first control signal from a first control signal terminal; N output circuits, wherein an i-th output circuit is used to provide an i-th output terminal with an i-th clock signal from an i-th clock signal terminal; a pull-down control circuit used to provide a pull-down node with a first power source signal from a first power source terminal, and to provide the pull-down node with a second power source signal from a second power source terminal; and a pull-down circuit used to provide each output terminal and the pull-up node with the second power source signal.
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公开(公告)号：US10692460B2
公开(公告)日：2020-06-23
申请号：US16320070
申请日：2018-03-08
Inventor： Lele Cong , Jian Sun , Wenwen Qin , Han Zhang
Abstract: Embodiments of the present application provide a display driving circuit, a method for controlling the same, and a display apparatus. The display driving circuit includes a plurality of function multiplexing circuits, and each of the plurality of function multiplexing circuits includes a data transmission terminal, an enabling signal terminal, a first signal terminal and a second signal terminal, and is configured to provide a test signal to the data transmission terminal and release static electricity at the data transmission terminal through the first signal terminal or the second signal terminal under control of the enabling signal terminal, the first signal terminal, and the second signal terminal, wherein the data transmission terminal is configured to be connected to at least one data line.
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公开(公告)号：US20190385688A1
公开(公告)日：2019-12-19
申请号：US16477362
申请日：2018-08-23
Inventor： Yishan Fu , Jun Fan , Fuqiang Li , Han Zhang
Abstract: A shift register unit, a driving method, a gate driving circuit and a display device are provided. The shift register unit includes: an input circuit used to provide a pull-up node with a first control signal from a first control signal terminal; N output circuits, wherein an i-th output circuit is used to provide an i-th output terminal with an i-th clock signal from an i-th clock signal terminal; a pull-down control circuit used to provide a pull-down node with a first power source signal from a first power source terminal, and to provide the pull-down node with a second power source signal from a second power source terminal; and a pull-down circuit used to provide each output terminal and the pull-up node with the second power source signal.
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10.发明申请公开(公告)号：US20180254091A1
公开(公告)日：2018-09-06
申请号：US15840030
申请日：2017-12-13
CPC classification number: G11C19/184 , G09G3/3677 , G09G2310/0286 , G09G2310/0289 , G11C19/28
Abstract: The present disclosure relates to a shift register unit and driving method thereof, a gate electrode driving circuit and a display apparatus, in the field of display technology. The shift register unit comprises an input circuit, an output circuit, a control circuit, a reset circuit, and a switch circuit. The switch circuit may control the second and third nodes to be disconnected when the electric potential of the input signal is the first electric potential (i.e., the effective electric potential). Thus, the following case can be avoided: when the second clock signal and the input signal have the first electric potential respectively, the second power source signal written into the third node by the second power source signal end is transmitted to the second node. As a result, the stability of the electric potential of the second node can be ensured. Further, as the reset circuit resets the first node and the output end under the control of the second node, after the electric potential of the second node stabilizes, the stability of the electric potential of the first node and the output end can be ensured.
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