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公开(公告)号：US10671224B2
公开(公告)日：2020-06-02
申请号：US15561559
申请日：2017-04-10
Inventor： Deshuai Wang , Xinyou Ji
Abstract: The present disclosure provides an in cell touch screen including a plurality of touch electrodes and a shade structure, wherein the shade structure includes a plurality of first shade bars arranged in parallel along a first direction and a plurality of second shade bars arranged in parallel along a second direction perpendicular to the first direction; and the first shade bars are conductive, and the touch electrodes are electrically connected to the first shade bars, respectively.
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公开(公告)号：US12140999B2
公开(公告)日：2024-11-12
申请号：US17925658
申请日：2021-12-20
Applicant: BOE Technology Group Co., Ltd.
Inventor： Deshuai Wang , Jian Sun , Zhen Wang , Yue Shan , Wei Yan , Jian Zhang , Han Zhang , Wenwen Qin , Yadong Zhang , Xiaoyan Yang , Keyan Liu , Hong Liu
IPC: G06F1/16
Abstract: A display panel includes: a base substrate including a display region and a fan-out region, and the fan-out region is located between the display region and a chip; a plurality of data wires/touch wires located in the fan-out region for respectively electrically connecting a plurality of data lines/touch signal lines with the chip. A portion of the plurality of data wires is located in a first conductive layer while a rest portion thereof is located in the second conductive layer. A portion of the plurality of touch wires is located in at least one of the first conductive layer and the second conductive layer while a rest portion thereof is located in the third conductive layer. A pitch between any two adjacent wires in the first/second/third conductive layer is a first/second/third wire pitch, respectively. The first wire pitch and the second wire pitch are smaller than the third wire pitch.
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公开(公告)号：US11961442B2
公开(公告)日：2024-04-16
申请号：US18032512
申请日：2020-10-21
Applicant: BOE Technology Group Co., Ltd.
Inventor： Wei Yan , Wenwen Qin , Yue Shan , Deshuai Wang , Jiguo Wang , Zhen Wang , Xiaoyan Yang , Han Zhang , Jian Zhang , Yadong Zhang , Jian Sun
CPC classification number: G09G3/20 , G11C19/28 , G09G2310/0286
Abstract: A shift register unit, a driving method, a drive circuit, and a display apparatus are disclosed. The shift register unit includes: a control circuit, which is configured to adjust signals of a first node and a second node according to an input signal end, a first control signal end, a second control signal end and a first reference signal end; a cascade circuit, which is configured to provide, according to the signal of the first node, a signal of a first cascade clock signal end to a cascade output end; and an output circuit, which is configured to provide, according to the signal of the first node, a signal of a control clock signal end to a drive output end, and provide, according to the signal of the second node, a signal of a second reference signal end to the drive output end.
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公开(公告)号：US11488512B2
公开(公告)日：2022-11-01
申请号：US16714385
申请日：2019-12-13
Inventor： Zhen Wang , Han Zhang , Zhengkui Wang , Wei Yan , Yun Qiao , Wenwen Qin , Xiaozhou Zhan , Jian Sun , Jian Zhang , Deshuai Wang
IPC: G09G3/20
Abstract: A display panel, a display device and a display control method thereof are provided in the present disclosure. The display panel includes: a time division multiplexing multiplexer (MUX) signal input circuit, which is connected with each of the plurality of signal lines, and configured to input data signals of each frame of display image to the plurality of signal lines, and for each frame of display image, input trigger signals corresponding to sub-pixel units of different colors to the plurality of signal lines in a time-sharing manner; among the plurality of signal lines, electrical signals on a plurality of adjacent first signal lines are arranged in sequence according to an order of positive, positive, negative and negative; among the plurality of signal lines, a first signal line has a spacing distance from adjacent signal lines less than a preset value.
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公开(公告)号：US12249383B2
公开(公告)日：2025-03-11
申请号：US17794991
申请日：2021-09-28
Applicant: BOE Technology Group Co., Ltd.
Inventor： Wei Yan , Zhen Wang , Wenwen Qin , Han Zhang , Deshuai Wang , Jian Zhang , Yue Shan , Xiaoyan Yang , Yadong Zhang , Jian Sun
Abstract: A shift register and a driving method therefor, a gate driving circuit and a display device are provided, wherein the shift register includes a pull-up control sub-circuit configured to provide a signal of a first signal terminal or a second signal terminal to a pull-up control node under control of a first input terminal and a second output terminal; the pull-down control sub-circuit is configured to provide a signal of a first power supply terminal or a second power supply terminal to a pull-down node under control of the pull-up control node, the first signal terminal, the second signal terminal, a first clock signal terminal and a second clock signal terminal; the output sub-circuit is configured to supply a signal of a third clock signal terminal to a first output terminal and a signal of a fourth clock signal terminal to the second output terminal.
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Patent Agency Ranking
公开(公告)号：US11984453B2
公开(公告)日：2024-05-14
申请号：US17622708
申请日：2021-01-29
Applicant: BOE Technology Group Co., Ltd.
Inventor： Jiguo Wang , Jian Sun , Zhao Zhang , Liang Tian , Weida Qin , Zhen Wang , Han Zhang , Wenwen Qin , Xiaoyan Yang , Yue Shan , Wei Yan , Jian Zhang , Deshuai Wang , Yadong Zhang , Jiantao Liu
IPC: G02F1/1362 , G02F1/1368 , H01L27/12
CPC classification number: H01L27/124 , G02F1/136209 , G02F1/136213 , G02F1/136222 , G02F1/13629 , G02F1/1368 , H01L27/1255
Abstract: An array substrate includes: a first substrate (10), including a plurality of sub-pixel regions (101) arranged in an array along a row direction (X) and a column direction (Y); a pixel circuit layer, including a plurality of sub-pixel circuits; a planarization layer (17), provided with a first via hole (170) located in the sub-pixel regions (101), and includes at least one pattern portion (171), the pattern portion (171) includes a plurality of pattern units (171a) arranged in an array along the row direction (X) and the column direction (Y); and a reflective electrode layer, wherein the reflective electrode layer includes a plurality of reflective electrodes (18) that are mutually disconnected, each of the reflective electrodes (18) is located in one of the sub-pixel regions (101) and is electrically connected to the sub-pixel circuit through the first via hole (170).
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公开(公告)号：US11875727B2
公开(公告)日：2024-01-16
申请号：US17593953
申请日：2020-12-22
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Zhen Wang , Jian Zhang , Jian Sun , Wei Yan , Deshuai Wang , Wenwen Qin , Jiguo Wang , Han Zhang , Yue Shan , Xiaoyan Yang , Yadong Zhang , Shijun Wang , Jiantao Liu
CPC classification number: G09G3/2096 , G09G2310/0283 , G09G2310/0286 , G09G2310/08 , G11C19/28
Abstract: The present disclosure provides a shift register, a gate driving circuit, a display panel, and a driving method thereof. The shift register includes: an input circuit; an output circuit; a first control circuit configured to provide a potential of a first control signal terminal to a pull-down node, and provide a potential of a reference signal terminal to the pull-down node according to the potential of the pull-up node; and a second control circuit connected to the pull-down node, a second control signal terminal, the output signal terminal, and the reference signal terminal, wherein the second control circuit is configured to pull down a potential of the output signal terminal during a display phase under the control of a potential of the pull-down node and a potential of the second control signal terminal, and pull up the potential of the output signal terminal in a power-off phase.
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公开(公告)号：US11921390B2
公开(公告)日：2024-03-05
申请号：US17427622
申请日：2020-10-22
Applicant: BOE Technology Group Co., Ltd.
Inventor： Jian Zhang , Zhen Wang , Deshuai Wang , Han Zhang , Wei Yan , Jian Sun
IPC: G02F1/1362
CPC classification number: G02F1/136295
Abstract: The present disclosure provides an array substrate, a manufacturing method thereof and a display device. The array substrate includes: a display area and a peripheral area surrounding the display area; the display area is provided with a plurality of gate lines and a plurality of data lines, the gate lines and the data lines are crossed to define a plurality of sub-pixel regions distributed in an array; a first electrode, the first electrode including a first portion located in the display area and a second portion located in the peripheral area; an electrode connection line, the electrode connection line is located in the peripheral area, the electrode connection line is electrically connected to the second portion; a plurality of compensation signal lines, at least part of the compensation signal lines are located in the display area, and the compensation signal lines are electrically connected to the first portion.
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公开(公告)号：US11901375B2
公开(公告)日：2024-02-13
申请号：US17765304
申请日：2021-04-13
Inventor： Yongbo Ju , Pengfei Cui , Jian Sun , Deshuai Wang , Xiangkai Shen , Jianbin Gao , Jiannan Wang , Guangshuai Wang
IPC: G02F1/1345 , H01L27/12 , G06F3/044 , G06F3/041 , G02F1/1333 , H01L23/00 , G02F1/1368
CPC classification number: H01L27/1244 , G02F1/13338 , G02F1/13458 , G06F3/0412 , G06F3/0445 , G06F3/04164 , H01L24/03 , H01L24/05 , H01L27/1259 , G02F1/13452 , G02F1/13685 , G06F2203/04103 , H01L24/06 , H01L2224/0345 , H01L2224/0362 , H01L2224/03614 , H01L2224/05008 , H01L2224/05013 , H01L2224/0518 , H01L2224/05073 , H01L2224/05124 , H01L2224/05138 , H01L2224/05147 , H01L2224/05166 , H01L2224/05548 , H01L2224/05553 , H01L2224/05566 , H01L2224/05573 , H01L2224/05686 , H01L2224/06165 , H01L2924/0106 , H01L2924/0132 , H01L2924/0549
Abstract: An array substrate has a display area and a bonding area located on a side of the display area. The array substrate includes a base, a plurality of first transistors, a plurality of conductive pins and a plurality of conductive electrodes. The plurality of first transistors are disposed on a side of the base and located in the display area; a first transistor includes a first gate, a first source and a first drain. The plurality of conductive pins are disposed on the side of the base and located in the bonding area, and are disposed in a same layer as the first gate. The plurality of conductive electrodes are each disposed on a respective one of surfaces of the plurality of conductive pins away from the base.
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公开(公告)号：US20220398968A1
公开(公告)日：2022-12-15
申请号：US17593953
申请日：2020-12-22
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Zhen Wang , Jian Zhang , Jian Sun , Wei Yan , Deshuai Wang , Wenwen Qin , Jiguo Wang , Han Zhang , Yue Shan , Xiaoyan Yang , Yadong Zhang , Shijun Wang , Jiantao Liu
IPC: G09G3/20
Abstract: The present disclosure provides a shift register, a gate driving circuit, a display panel, and a driving method thereof. The shift register includes: an input circuit; an output circuit; a first control circuit configured to provide a potential of a first control signal terminal to a pull-down node, and provide a potential of a reference signal terminal to the pull-down node according to the potential of the pull-up node; and a second control circuit connected to the pull-down node, a second control signal terminal, the output signal terminal, and the reference signal terminal, wherein the second control circuit is configured to pull down a potential of the output signal terminal during a display phase under the control of a potential of the pull-down node and a potential of the second control signal terminal, and pull up the potential of the output signal terminal in a power-off phase.
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