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公开(公告)号:US20220398968A1
公开(公告)日:2022-12-15
申请号:US17593953
申请日:2020-12-22
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor: Zhen Wang , Jian Zhang , Jian Sun , Wei Yan , Deshuai Wang , Wenwen Qin , Jiguo Wang , Han Zhang , Yue Shan , Xiaoyan Yang , Yadong Zhang , Shijun Wang , Jiantao Liu
IPC: G09G3/20
Abstract: The present disclosure provides a shift register, a gate driving circuit, a display panel, and a driving method thereof. The shift register includes: an input circuit; an output circuit; a first control circuit configured to provide a potential of a first control signal terminal to a pull-down node, and provide a potential of a reference signal terminal to the pull-down node according to the potential of the pull-up node; and a second control circuit connected to the pull-down node, a second control signal terminal, the output signal terminal, and the reference signal terminal, wherein the second control circuit is configured to pull down a potential of the output signal terminal during a display phase under the control of a potential of the pull-down node and a potential of the second control signal terminal, and pull up the potential of the output signal terminal in a power-off phase.
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公开(公告)号:US10269282B2
公开(公告)日:2019-04-23
申请号:US15759722
申请日:2017-09-13
Inventor: Yue Shan , Jun Fan , Jiguo Wang , Yishan Fu , Mingchao Ma
Abstract: A shift register, a gate driving circuit, a display panel and a driving method. The shift register includes: an input circuit, an output circuit, a pull-up-node pull-down circuit, a first control circuit, a second control circuit and an output pull-down circuit. The first control circuit is configured to write a fourth clock signal into a first pull-down node and write a first power voltage into a second pull-down node responsive to a first control signal, and to write the first power voltage into the first pull-down node responsive to a voltage of a pull-up node. The second control circuit is configured to write the fourth clock signal into the second pull-down node and write the first power voltage into the first pull-down node responsive to a second control signal, and to write the first power voltage into the second pull-down node responsive to the voltage of the pull-up node.
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公开(公告)号:US12140999B2
公开(公告)日:2024-11-12
申请号:US17925658
申请日:2021-12-20
Applicant: BOE Technology Group Co., Ltd.
Inventor: Deshuai Wang , Jian Sun , Zhen Wang , Yue Shan , Wei Yan , Jian Zhang , Han Zhang , Wenwen Qin , Yadong Zhang , Xiaoyan Yang , Keyan Liu , Hong Liu
IPC: G06F1/16
Abstract: A display panel includes: a base substrate including a display region and a fan-out region, and the fan-out region is located between the display region and a chip; a plurality of data wires/touch wires located in the fan-out region for respectively electrically connecting a plurality of data lines/touch signal lines with the chip. A portion of the plurality of data wires is located in a first conductive layer while a rest portion thereof is located in the second conductive layer. A portion of the plurality of touch wires is located in at least one of the first conductive layer and the second conductive layer while a rest portion thereof is located in the third conductive layer. A pitch between any two adjacent wires in the first/second/third conductive layer is a first/second/third wire pitch, respectively. The first wire pitch and the second wire pitch are smaller than the third wire pitch.
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公开(公告)号:US11961442B2
公开(公告)日:2024-04-16
申请号:US18032512
申请日:2020-10-21
Applicant: BOE Technology Group Co., Ltd.
Inventor: Wei Yan , Wenwen Qin , Yue Shan , Deshuai Wang , Jiguo Wang , Zhen Wang , Xiaoyan Yang , Han Zhang , Jian Zhang , Yadong Zhang , Jian Sun
CPC classification number: G09G3/20 , G11C19/28 , G09G2310/0286
Abstract: A shift register unit, a driving method, a drive circuit, and a display apparatus are disclosed. The shift register unit includes: a control circuit, which is configured to adjust signals of a first node and a second node according to an input signal end, a first control signal end, a second control signal end and a first reference signal end; a cascade circuit, which is configured to provide, according to the signal of the first node, a signal of a first cascade clock signal end to a cascade output end; and an output circuit, which is configured to provide, according to the signal of the first node, a signal of a control clock signal end to a drive output end, and provide, according to the signal of the second node, a signal of a second reference signal end to the drive output end.
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公开(公告)号:US11329508B2
公开(公告)日:2022-05-10
申请号:US16640211
申请日:2019-03-20
Inventor: Yanwei Ren , Yue Shan , Yu Feng , Min Liu
IPC: H02J50/10 , G02F1/1333 , G02F1/1335 , G02F1/1343 , G02F1/1345 , G02F1/1362 , G06F3/041 , H02J7/02 , H04B5/00 , H01F38/14
Abstract: A display substrate, a display device and a wireless charging method are provided. The display substrate includes: a display area and a peripheral area located outside the display area. The peripheral area includes a circuit binding area. The display substrate includes a base substrate and a wireless charging antenna disposed on the base substrate. The wireless charging antenna includes a power receiving coil and a connection lead. The connection lead is connected to the power receiving coil, and the power receiving coil is connected to the circuit binding area.
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公开(公告)号:US10950319B2
公开(公告)日:2021-03-16
申请号:US16339752
申请日:2018-09-14
Inventor: Yue Shan , Jiguo Wang , Jun Fan
Abstract: A shift register and a corresponding driving method, a gate driving circuit and a display device, the shift registers includes an input and reset circuit, a first output circuit, a second output circuit, a first pull-down circuit and a second pull-down circuit; the first output circuit and the second output circuit output gate driving signals according to potentials at a first clock signal terminal and a second clock signal terminal respectively, the first pull-down circuit and the second pull-down circuit reset potentials at a pull up node, a first output terminal and a second output terminal according to potentials at a first pull-down node a second pull-down node respectively.
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公开(公告)号:US20190189039A1
公开(公告)日:2019-06-20
申请号:US16145396
申请日:2018-09-28
Inventor: Yishan Fu , Jun Fan , Fuqiang Li , Jiguo Wang , Yue Shan , Taiyang Liu
CPC classification number: G09G3/20 , G09G2310/0267 , G09G2310/0286 , G09G2310/08 , G09G2320/0252 , G11C19/28
Abstract: A shift register circuit, a scan driving circuit, a display device and method for driving the scan driving circuit are provided. The shift register circuit includes: an input circuit for providing an active level for the first node upon receiving the active level of scan trigger signal; a trigger circuit for outputting the active level of scan trigger signal at the second node when first node is at the active level and a first clock signal is at first level; a locking circuit for locking the level of first node as inactive level when a first control signal is at the active level; and an output circuit for outputting a gate turn-on voltage during a period in which the second node is at an active level of the scan trigger signal, and outputting a voltage same as voltage of a second control signal during other periods other than the period.
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公开(公告)号:US12249383B2
公开(公告)日:2025-03-11
申请号:US17794991
申请日:2021-09-28
Applicant: BOE Technology Group Co., Ltd.
Inventor: Wei Yan , Zhen Wang , Wenwen Qin , Han Zhang , Deshuai Wang , Jian Zhang , Yue Shan , Xiaoyan Yang , Yadong Zhang , Jian Sun
Abstract: A shift register and a driving method therefor, a gate driving circuit and a display device are provided, wherein the shift register includes a pull-up control sub-circuit configured to provide a signal of a first signal terminal or a second signal terminal to a pull-up control node under control of a first input terminal and a second output terminal; the pull-down control sub-circuit is configured to provide a signal of a first power supply terminal or a second power supply terminal to a pull-down node under control of the pull-up control node, the first signal terminal, the second signal terminal, a first clock signal terminal and a second clock signal terminal; the output sub-circuit is configured to supply a signal of a third clock signal terminal to a first output terminal and a signal of a fourth clock signal terminal to the second output terminal.
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公开(公告)号:US11984453B2
公开(公告)日:2024-05-14
申请号:US17622708
申请日:2021-01-29
Applicant: BOE Technology Group Co., Ltd.
Inventor: Jiguo Wang , Jian Sun , Zhao Zhang , Liang Tian , Weida Qin , Zhen Wang , Han Zhang , Wenwen Qin , Xiaoyan Yang , Yue Shan , Wei Yan , Jian Zhang , Deshuai Wang , Yadong Zhang , Jiantao Liu
IPC: G02F1/1362 , G02F1/1368 , H01L27/12
CPC classification number: H01L27/124 , G02F1/136209 , G02F1/136213 , G02F1/136222 , G02F1/13629 , G02F1/1368 , H01L27/1255
Abstract: An array substrate includes: a first substrate (10), including a plurality of sub-pixel regions (101) arranged in an array along a row direction (X) and a column direction (Y); a pixel circuit layer, including a plurality of sub-pixel circuits; a planarization layer (17), provided with a first via hole (170) located in the sub-pixel regions (101), and includes at least one pattern portion (171), the pattern portion (171) includes a plurality of pattern units (171a) arranged in an array along the row direction (X) and the column direction (Y); and a reflective electrode layer, wherein the reflective electrode layer includes a plurality of reflective electrodes (18) that are mutually disconnected, each of the reflective electrodes (18) is located in one of the sub-pixel regions (101) and is electrically connected to the sub-pixel circuit through the first via hole (170).
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公开(公告)号:US11875727B2
公开(公告)日:2024-01-16
申请号:US17593953
申请日:2020-12-22
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor: Zhen Wang , Jian Zhang , Jian Sun , Wei Yan , Deshuai Wang , Wenwen Qin , Jiguo Wang , Han Zhang , Yue Shan , Xiaoyan Yang , Yadong Zhang , Shijun Wang , Jiantao Liu
CPC classification number: G09G3/2096 , G09G2310/0283 , G09G2310/0286 , G09G2310/08 , G11C19/28
Abstract: The present disclosure provides a shift register, a gate driving circuit, a display panel, and a driving method thereof. The shift register includes: an input circuit; an output circuit; a first control circuit configured to provide a potential of a first control signal terminal to a pull-down node, and provide a potential of a reference signal terminal to the pull-down node according to the potential of the pull-up node; and a second control circuit connected to the pull-down node, a second control signal terminal, the output signal terminal, and the reference signal terminal, wherein the second control circuit is configured to pull down a potential of the output signal terminal during a display phase under the control of a potential of the pull-down node and a potential of the second control signal terminal, and pull up the potential of the output signal terminal in a power-off phase.
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