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公开(公告)号：US20240363737A1
公开(公告)日：2024-10-31
申请号：US18769204
申请日：2024-07-10
Inventor： Jun Liu , Luke Ding , Jingang Fang , Bin Zhou , Leilei Cheng , Wei Li
IPC: H01L29/66 , H01L21/027 , H01L21/311 , H01L21/3213 , H01L21/44 , H01L21/475 , H01L21/4757 , H01L21/4763 , H01L27/12 , H01L29/40 , H01L29/417 , H01L29/786
CPC classification number: H01L29/66969 , H01L21/0274 , H01L21/31116 , H01L21/31144 , H01L21/32139 , H01L21/44 , H01L21/475 , H01L21/47573 , H01L21/47635 , H01L27/1288 , H01L29/401 , H01L29/7869 , H01L29/41733 , H01L29/78633
Abstract: Provided are a manufacturing method of a display substrate, a display substrate, and a display device. The display substrate includes: a base substrate; and a top-gate type thin film transistor located on a side of the base substrate, the top-gate type thin film transistor comprises an active layer, a gate insulation layer and a gate electrode sequentially disposed in a direction away from the base substrate. A side surface of the gate insulation layer close to the gate electrode extends beyond an edge of the gate electrode in a direction parallel to the base substrate, and a side surface of the active layer close to the gate insulation layer extends beyond an edge of the gate insulation layer in the direction parallel to the base substrate.
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公开(公告)号：US20210124226A1
公开(公告)日：2021-04-29
申请号：US16964278
申请日：2019-12-13
Inventor： Leilei Cheng , Jingang Fang , Luke Ding , Jun Liu , Wei Li , Bin Zhou
IPC: G02F1/1362 , H01L21/768 , H01L23/532 , H01L27/12
Abstract: A method of manufacturing an array substrate is provided, which comprises: forming a first metal layer and an insulating layer in sequence on a base substrate, the insulating layer covering the first metal layer; forming an etch barrier layer on the insulating layer; etching the etching barrier layer and the insulating layer multiple times, wherein an effective blocking area of the etching barrier layer decreases successively in each etching to form a connection hole penetrating the insulating layer, the connection hole includes a plurality of via holes connected in sequence, and a slope angle of a hole wall of each via hole is smaller than a preset slope angle; and forming a second metal layer, the second metal layer being connected to the first metal layer through the connection hole.
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公开(公告)号：US10833104B2
公开(公告)日：2020-11-10
申请号：US15745773
申请日：2017-07-20
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Jingang Fang , Youngsun Song , Hongda Sun , Wei Li
IPC: H01L27/12 , H01L29/66 , H01L29/786
Abstract: The present disclosure provides a fabricating method of an array substrate, comprising: forming a pattern comprising a light shading member; spreading an organic material solution; solidifying the organic material solution, to form a buffer layer; forming a pattern of an active layer on the buffer layer, wherein a position of the active layer corresponds to a position of the light shading member; and forming a gate pattern, where the gate pattern is located on the active layer and is insulated from the active layer. Correspondingly, the present disclosure further provides an array substrate and a display device.
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公开(公告)号：US10090368B2
公开(公告)日：2018-10-02
申请号：US14785830
申请日：2015-02-27
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Jingang Fang , Longbao Xin , Hongda Sun
Abstract: The present invention provides an array substrate and a manufacturing method thereof, and a display apparatus; and it relates to the field of display. The array substrate includes a first thin film transistor and a first electrode which are formed on a substrate. The first thin film transistor includes a gate, a gate insulating layer, an active layer, and an etch stop layer. The etch stop layer is formed with first via holes, and the etch stop layer and the gate insulating layer are formed with a second via hole at a position corresponding to the first electrode. A maximal diameter of the first via holes is not greater than a minimal diameter of the second via hole.
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5.发明授权公开(公告)号：US10038097B2
公开(公告)日：2018-07-31
申请号：US15504030
申请日：2016-08-16
Applicant: Boe Technology Group Co., Ltd.
Inventor： Jingang Fang , Youngsuk Song , Hongda Sun , Wei Li
IPC: H01L29/786 , H01L51/00 , H01L27/32 , H01L27/12 , H01L51/56
CPC classification number: H01L29/78627 , H01L27/1214 , H01L27/1248 , H01L27/1288 , H01L27/322 , H01L27/3246 , H01L27/3258 , H01L27/3276 , H01L27/3295 , H01L51/0011 , H01L51/0017 , H01L51/56
Abstract: A light emitting diode display substrate, a method of manufacturing the same, and a display device are provided. The method includes: forming a planarization layer and a photoresist layer in sequence on a substrate on which a thin film transistor is formed, a light sensitivity of the planarization layer being higher than a light sensitivity of the photoresist layer; etching the planarization layer and the photoresist layer simultaneously, such that a pixel defining pattern is formed through a removed portion of the photoresist layer, and an anode via pattern is formed at a position of the planarization layer corresponding to the pixel defining pattern; forming an anode pattern layer on the substrate on which the above steps were performed, wherein the anode pattern layer comprises a plurality of anodes, such that the planarization layer located at edges of the anode via pattern covers edges of the anodes.
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Patent Agency Ranking
6.发明授权公开(公告)号：US09461070B2
公开(公告)日：2016-10-04
申请号：US14377946
申请日：2013-12-11
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Yanzhao Li , Gang Wang , Jingang Fang
IPC: H01L35/24 , H01L27/12 , H01L29/786 , H01L29/66 , H01L29/24 , H01L29/20 , H01L29/04 , H01L21/02 , H01L21/477 , H01L21/461 , H01L21/324
CPC classification number: H01L27/1222 , H01L21/02521 , H01L21/02543 , H01L21/02565 , H01L21/02592 , H01L21/02631 , H01L21/324 , H01L21/461 , H01L21/477 , H01L27/1259 , H01L29/04 , H01L29/20 , H01L29/24 , H01L29/26 , H01L29/66742 , H01L29/66969 , H01L29/786 , H01L29/78681 , H01L29/78693 , H01L29/78696
Abstract: A thin film transistor is provided. An active layer (3) of the thin film transistor is made of an amorphous phosphide semiconductor material. Due to high carrier mobility of the phosphide semiconductor material, a thin film transistor with a high carrier mobility can be obtained by employing the amorphous phosphide semiconductor material to prepare the active layer of the thin film transistor. A method for manufacturing such a thin film transistor, and an array substrate and a display panel each comprising such a thin film transistor, are further provided.
Abstract translation: 提供薄膜晶体管。 薄膜晶体管的有源层（3）由非晶磷化物半导体材料制成。 由于磷化物半导体材料的高载流子迁移率，通过采用非晶磷化物半导体材料制备薄膜晶体管的有源层，可以获得具有高载流子迁移率的薄膜晶体管。 还提供了一种制造这种薄膜晶体管的方法，以及包括这种薄膜晶体管的阵列基板和显示面板。
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7.发明授权公开(公告)号：US11910636B2
公开(公告)日：2024-02-20
申请号：US17481327
申请日：2021-09-22
Inventor： Qinghe Wang , Jun Cheng , Tongshang Su , Ning Liu , Haitao Wang , Yongchao Huang , Jingang Fang , Liusong Ni , Liangchen Yan
IPC: H01L29/08 , H10K50/824 , H10K77/10 , H10K102/10 , H10K102/00
CPC classification number: H10K50/824 , H10K77/111 , H10K2102/103 , H10K2102/311
Abstract: Provided are a display substrate and a display apparatus. The display substrate includes a base substrate, and an auxiliary cathode structure located on a side of the base substrate, the auxiliary cathode structure including a first conductive layer, an intermediate support layer, and a second conductive layer. In an implementation, a side of the intermediate support layer close to the first conductive layer includes any one or more of first protrusions and first grooves, and a side of the first conductive layer close to the intermediate support layer includes any one or more of second grooves engaged with the first protrusions and second protrusions engaged with the first grooves which are correspondingly disposed.
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8.发明授权公开(公告)号：US11765920B2
公开(公告)日：2023-09-19
申请号：US17395179
申请日：2021-08-05
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Huifeng Wang , Wang Zhang , Jingang Fang
IPC: H01L51/50 , H10K50/13 , H10K50/822 , H10K59/122 , H10K71/00 , H10K71/60 , H10K71/16 , H10K71/20 , H10K59/12
CPC classification number: H10K50/131 , H10K50/822 , H10K59/122 , H10K71/00 , H10K71/164 , H10K71/166 , H10K71/233 , H10K71/60 , H10K59/1201
Abstract: The present disclosure relates to an organic electroluminescent display panel, a method of manufacturing the same, and a display device that can alleviate or avoid the occurrence of pixel crosstalk problems due to lateral conduction of the charge generation layer. An organic electroluminescent display panel is provided which comprises: a substrate; an anode layer and a pixel defining layer over the substrate, the pixel defining layer defining pixel units, wherein a recess is provided in the pixel defining layer between adjacent pixel units; a stack of organic electroluminescent units over the anode layer and the pixel defining layer, the stack comprising at least two organic electroluminescent units and a charge generation layer disposed between organic electroluminescent units which are adjacent to each other; a cathode layer over the stack, wherein the corresponding charge generation layers of the adjacent pixel units are disconnected at the recesses, and wherein the cathode layer is continuous at the recess.
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公开(公告)号：US20220077255A1
公开(公告)日：2022-03-10
申请号：US17417334
申请日：2020-11-05
Inventor： Wei Li , Jingjing XIA , Bin Zhou , Yang Zhang , Guangyao Li , Wei Song , Xuanang Wang , Qinghe Wang , Liusong Ni , Jun Liu , Liangchen Yan , Ming Wang , Jingang Fang
Abstract: The present disclosure provides an array substrate, a method for manufacturing the array substrate, a display panel and a display device. The array substrate includes: a substrate; a planarization layer on a side of the substrate; a pixel defining layer configured to define a pixel opening region and located on a side of the planarization layer away from the substrate; an anode in the pixel opening region and on a side of the planarization layer away from the substrate. The array substrate further includes an intermediate insulation layer between the planarization layer and the pixel defining layer. The intermediate insulation layer has a chemical polarity between a chemical polarity of the planarization layer and a chemical polarity of the pixel defining layer.
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公开(公告)号：US20220020867A1
公开(公告)日：2022-01-20
申请号：US17449607
申请日：2021-09-30
Inventor： Jun Liu , Luke Ding , Jingang Fang , Bin Zhou , Leilei Cheng , Wei Li
IPC: H01L29/66 , H01L29/786 , H01L21/44 , H01L21/4763 , H01L21/475 , H01L29/40 , H01L21/4757 , H01L27/12 , H01L21/027 , H01L21/311 , H01L21/3213
Abstract: A manufacturing method of a display substrate, a display substrate, and a display device. The manufacturing method includes: forming an active layer; forming a gate insulation film layer, a gate film layer and a photoresist film layer; exposing the photoresist film layer to a light and developing the exposed photoresist film layer until the developed photoresist film layer has a thickness of 1.8-2.2 μm and a slope angle not less than 70°; over-etching the gate film layer to form a gate electrode, an orthographic projection of the gate electrode being located within a region of an orthographic projection of the developed photoresist film layer; over-etching the gate insulation film layer by a gaseous corrosion method to form a gate insulation layer; peeling off the photoresist film layer remaining on a surface of the gate electrode; and performing a conductive treatment to the active layer.
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