公开(公告)号：US5982659A

公开(公告)日：1999-11-09

申请号：US779998

申请日：1996-12-23

Applicant: V. Swamy Irrinki ,  Thomas R. Wik ,  Raymond T. Leung ,  Ashok Kapoor ,  Alex Owens

Inventor： V. Swamy Irrinki ,  Thomas R. Wik ,  Raymond T. Leung ,  Ashok Kapoor ,  Alex Owens

IPC: G11C11/56 ,  G11C17/00 ,  G11C17/14

CPC classification number: G11C17/00 ,  G11C11/56 ,  G11C11/5692 ,  G11C7/16

Abstract: A process which enables storage of more than two logic states in a memory cell. In one embodiment, a via is used to couple a diode between a word read line and a data read line. The via has a resistance which is set to one of a plurality of values at the time of manufacture. When the word read line is asserted, the voltage drop sustained across the via is indicative of the stored logic state. An analog-to-digital (A/D) converter is coupled to the data read line so as to sense the voltage drop and determine the state represented. Since the additional logic states may be used to represent additional information bits, this memory circuit increases the number of bits that may be stored per memory cell, thereby increasing the storage density and reducing the cost per bit.

Abstract translation: 能够在存储器单元中存储多于两个逻辑状态的过程。 在一个实施例中，通孔用于在字读取线和数据读取线之间耦合二极管。 通孔具有在制造时被设置为多个值之一的电阻。 当字读取线被断言时，贯穿通孔的电压降指示存储的逻辑状态。 模数（A / D）转换器耦合到数据读取线，以便感测电压降并确定所表示的状态。 由于附加逻辑状态可用于表示附加信息位，所以该存储器电路增加了每个存储单元可以存储的位数，由此增加了存储密度并降低了每位的成本。

公开(公告)号：US5784328A

公开(公告)日：1998-07-21

申请号：US779999

申请日：1996-12-23

Applicant: V. Swamy Irrinki ,  Ashok Kapoor ,  Raymond Leung ,  Alex Owens ,  Thomas R. Wik

Inventor： V. Swamy Irrinki ,  Ashok Kapoor ,  Raymond Leung ,  Alex Owens ,  Thomas R. Wik

IPC: G11C11/406 ,  G11C11/56 ,  G11C7/00

CPC classification number: G11C7/04 ,  G11C11/406 ,  G11C11/40626 ,  G11C11/565 ,  G11C16/3418 ,  G11C16/3431

Abstract: A DRAM memory array including a temperature sensor for adjusting a refresh rate depending upon temperature. The DRAM memory array includes a plurality of memory cells, each configured to allow storage and retrieval of more than two discrete memory states. A refresh circuit is coupled to the memory array for periodically refreshing the discrete storage state of each memory cell. The temperature sensor is situated on the same semiconductor die upon which the memory array is fabricated, and generates a signal indicative of the temperature of the semiconductor die. A control circuit receives the signal from the temperature sensor and responsively generates a refresh rate signal which is provided to control the refresh rate of the refresh circuit. In one specific implementation, a ROM look-up table is coupled to the control circuit and includes a plurality of entries which indicate the desired refresh rates for particular temperatures. By controlling the refresh rate dependent upon the temperature of the semiconductor die, proper state retention is ensured within each of the memory cells while allowing performance to be optimized.

Abstract translation: 一种DRAM存储器阵列，包括用于根据温度调节刷新率的温度传感器。 DRAM存储器阵列包括多个存储器单元，每个存储器单元被配置为允许存储和检索多于两个的离散存储器状态。 刷新电路耦合到存储器阵列，用于周期性地刷新每个存储单元的离散存储状态。 温度传感器位于制造存储器阵列的相同的​​半导体管芯上，并且产生表示半导体管芯的温度的信号。 控制电路接收来自温度传感器的信号，并且响应地产生刷新率信号，该信号被提供以控制刷新电路的刷新率。 在一个具体实现中，ROM查找表耦合到控制电路，并且包括指示特定温度的期望刷新率的多个条目。 通过根据半导体管芯的温度控制刷新率，确保每个存储单元内的适当的状态保持，同时允许优化性能。

公开(公告)号：US5771187A

公开(公告)日：1998-06-23

申请号：US779994

申请日：1996-12-23

Applicant: Ashok Kapoor

Inventor： Ashok Kapoor

IPC: G11C11/56 ,  G11C11/24

CPC classification number: G11C11/565 ,  G11C7/16

Abstract: A semiconductor memory device which includes a word line, a bit line and a storage capacitor having first and second ends. A pair of FEATS each having gates coupled to the word line and one side coupled to the bit line. The other side of each FEAT is coupled to a storage capacitor upon which a selected one of four potential levels, corresponding to stored values of zero, one, two, or three, can be stored and thereafter read. One of the FEATS has a thicker gate oxide than the other and thus a higher threshold voltage. Voltage stored on the capacitor is read in two cycles thereby producing in the first cycle a high level pulse, a low level pulse, or no pulse and in the second cycle, a low level pulse or no pulse, depending upon the level of charge stored on the capacitor.

Abstract translation: 一种半导体存储器件，包括字线，位线和具有第一和第二端的存储电容器。 一对FEATS，每一个具有耦合到字线的栅极和耦合到位线的一侧。 每个FEAT的另一侧耦合到存储电容器，在存储电容器上可以存储对应于存储的零，一个，二个或三个值的四个电位电平中的所选择的一个，然后读取。 其中一个FEATS具有比另一个更厚的栅极氧化物，因此具有较高的阈值电压。 存储在电容器上的电压被读取两个周期，从而在第一周期中产生高电平脉冲，低电平脉冲或无脉冲，并且在第二周期中，根据存储的电荷电平产生低电平脉冲或无脉冲 在电容上。

公开(公告)号：US5061986A

公开(公告)日：1991-10-29

申请号：US476149

申请日：1990-02-05

Applicant: Madhukar Vora ,  Greg Burton ,  Ashok Kapoor

Inventor： Madhukar Vora ,  Greg Burton ,  Ashok Kapoor

IPC: H01L21/285 ,  H01L21/768 ,  H01L21/8249 ,  H01L23/485 ,  H01L23/528 ,  H01L23/532 ,  H01L27/108 ,  H01L27/11

CPC classification number: H01L21/28518 ,  H01L21/76877 ,  H01L21/76889 ,  H01L21/8249 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53271 ,  H01L27/10805 ,  H01L27/1104 ,  H01L2924/0002 ,  H01L2924/3011

Abstract: There is disclosed herein a bipolar transistor structure having a self aligned extended silicide base contact. The contact extends to the position of a base contact window located outside the perimeter of the isolation island on a contact pad formed over the field oxide. This allows the size of the isolation island to be kept smaller and allows a smaller extrinsic base regions to be formed. The base contact is formed of titanium and titanium silicide where the titanium/silicide boundary is self aligned with the edge of the device isolation island. The silicide is formed by reacting the titanium which completely covers the exposed epitaxial silicon inside the isolation island. An anisotropically etched oxide sidewall spacer insulates the silicide from the sidewall of the silicide-covered, polysilicon emitter contact.

Abstract translation: 本文公开了具有自对准的延伸硅化物基极接触的双极晶体管结构。 接触件延伸到位于场氧化物上形成的接触垫上的位于隔离岛的周边外部的基底接触窗口的位置。 这允许隔离岛的尺寸保持较小并且允许形成更小的非本征基区。 基极接触由钛和硅化钛形成，其中钛/硅化物边界与器件隔离岛的边缘自对准。 硅化物通过使完全覆盖隔离岛内的暴露的外延硅的钛反应而形成。 各向异性蚀刻的氧化物侧壁间隔物将硅化物与硅化物覆盖的多晶硅发射极接触的侧壁绝缘。

公开(公告)号：US20070126478A1

公开(公告)日：2007-06-07

申请号：US11635004

申请日：2006-12-07

Applicant: Ashok Kapoor

Inventor： Ashok Kapoor

IPC: H03K19/0175

CPC classification number: H03K19/0941 ,  H01L27/098 ,  H01L29/66901 ,  H01L29/808 ,  H03K2217/0018

Abstract: A method for using an inverter with a pair of complementary junction field effect transistors (CJFET) with a small linewidth is provided. The method includes having an input capacitance for said CJFET inverter to be less than the corresponding input capacitance of a CMOS inverter of similar linewidth. The CJFET operates at a power supply with a lesser value than the voltage drop across a forward-biased diode having a reduced switching power as compared to said CMOS inverter and having a propagation delay for said CJFET inverter that is at least comparable to the corresponding delay of said CMOS inverter.

Abstract translation: 提供了一种使用具有小线宽的一对互补结场效应晶体管（CJFET）的逆变器的方法。 该方法包括使所述CJFET反相器的输入电容小于类似线宽的CMOS反相器的相应输入电容。 与所述CMOS反相器相比，CJFET工作在比具有降低的开关功率的正向偏置二极管的电压降低的电源，并且具有至少与相应延迟相当的所述CJFET反相器的传播延迟 的CMOS反相器。

公开(公告)号：US20070069306A1

公开(公告)日：2007-03-29

申请号：US11533332

申请日：2006-09-19

Applicant: Ashok Kapoor ,  Robert Strain ,  Reuven Marko

Inventor： Ashok Kapoor ,  Robert Strain ,  Reuven Marko

IPC: H01L29/94

CPC classification number: H01L27/0629 ,  H01L27/0727 ,  H01L27/1203 ,  H01L29/78 ,  H03K19/0005 ,  H03K19/0016 ,  H03K19/00361

Abstract: An apparatus and method of manufacture for metal-oxide semiconductor (MOS) transistors is disclosed. Devices in accordance with the invention are operable at voltages below 2V. The devices are area efficient, have improved drive strength, and have reduced leakage current. A dynamic threshold voltage control scheme comprised of a forward biased diode in parallel with a capacitor is used, implemented without changing the existing MOS technology process. This scheme controls the threshold voltage of each transistor. In the OFF state, the magnitude of the threshold voltage of the transistor increases, keeping the transistor leakage to a minimum. In the ON state, the magnitude of the threshold voltage decreases, resulting in increased drive strength. The invention is particularly useful in MOS technology for both bulk and silicon on insulator (SOI) CMOS. The use of reverse biasing of the well, in conjunction with the above construct to further decrease leakage in a MOS transistor, is also shown.

Abstract translation: 公开了一种用于金属氧化物半导体（MOS）晶体管的装置和制造方法。 根据本发明的装置可在低于2V的电压下工作。 这些器件具有区域有效性，具有改进的驱动强度，并且具有减小的漏电流。 使用包括与电容器并联的正向偏置二极管的动态阈值电压控制方案，而不改变现有的MOS技术过程。 该方案控制每个晶体管的阈值电压。 在OFF状态下，晶体管的阈值电压的大小增加，保持晶体管漏电量最小。 在ON状态下，阈值电压的大小减小，导致驱动强度增加。 本发明在用于体积和绝缘体上硅（SOI）CMOS的MOS技术中特别有用。 还示出了与上述结构一起使用阱的反向偏置以进一步减小MOS晶体管中的泄漏。

公开(公告)号：US6005264A

公开(公告)日：1999-12-21

申请号：US396541

申请日：1995-03-01

Applicant: Ashok Kapoor

Inventor： Ashok Kapoor

IPC: H01L21/822 ,  H01L21/8238 ,  H01L27/04 ,  H01L27/092 ,  H01L27/118 ,  H01L27/10 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC classification number: H01L27/11807 ,  H01L27/0922

Abstract: A microelectronic integrated circuit includes a semiconductor substrate, and a plurality of CMOS microelectronic devices formed on the substrate. Each device includes a hexagonal ANY element of a first conductivity type (PMOS or NMOS), and a hexagonal ALL element of a second conductivity type (NMOS or PMOS), the ANY and ALL elements each having a plurality of inputs and an output that are electrically interconnected respectively. The ANY element is basically an OR element, and the ALL element is basically an AND element. However, the power supply connections and the selection of conductivity type (NMOS or PMOS) for the ANY and ALL elements can be varied to provide the device as having a desired NAND, AND, NOR or OR configuration, in which the ANY element acts as a pull-up and the ALL element acts as a pull-down, or vice-versa.

Abstract translation: 微电子集成电路包括半导体衬底和形成在衬底上的多个CMOS微电子器件。 每个器件包括第一导电类型（PMOS或NMOS）的六边形ANY元件和第二导电类型（NMOS或PMOS）的六边形ALL元件，每个ANY和ALL元件都具有多个输入端和输出端 电连接。 ANY元素基本上是一个OR元素，ALL元素基本上是AND元素。 然而，可以改变ANY和ALL元件的电源连接和导电类型（NMOS或PMOS）的选择，以使器件具有所需的NAND，AND，NOR或OR配置，其中ANY元件作为 上拉和ALL元素作为下拉，反之亦然。

公开(公告)号：US5847990A

公开(公告)日：1998-12-08

申请号：US779993

申请日：1996-12-23

Applicant: V. Swamy Irrinki ,  Ashok Kapoor ,  Raymond T. Leung ,  Alex Owens ,  Thomas R. Wik

Inventor： V. Swamy Irrinki ,  Ashok Kapoor ,  Raymond T. Leung ,  Alex Owens ,  Thomas R. Wik

IPC: G11C11/41 ,  G11C11/56 ,  G11C11/00

CPC classification number: G11C11/5621 ,  G11C11/412 ,  G11C7/16

Abstract: A memory circuit which enables storage of three logic states in a memory cell. Since the additional logic states may be used to represent additional information bits, this memory circuit increases the number of bits that may be stored per memory cell, thereby increasing the storage density and reducing the cost per bit. The disclosed memory circuit comprises an analog-to-digital converter coupled to detect a current through a transistor in a memory cell. The current is determined by the state of a tri-state flip-flop. By enabling the current to be detected as positive, negative, or zero, it becomes possible to represent more than one bit of information with the state of the flip-flop.

Abstract translation: 一种能够在存储单元中存储三种逻辑状态的存储电路。 由于附加逻辑状态可用于表示附加信息位，所以该存储器电路增加了每个存储单元可以存储的位数，由此增加了存储密度并降低了每位的成本。 所公开的存储器电路包括耦合以检测通过存储器单元中的晶体管的电流的模拟 - 数字转换器。 电流由三态触发器的状态决定。 通过使电流被检测为正，负或零，可以用触发器的状态表示多于一个位的信息。

公开(公告)号：US20060202307A1

公开(公告)日：2006-09-14

申请号：US11078830

申请日：2005-03-11

Applicant: Ashok Kapoor

Inventor： Ashok Kapoor

IPC: H01L27/082

CPC classification number: H01L29/1004 ,  H01L29/167 ,  H01L29/66992 ,  H01L29/73

Abstract: A bipolar transistor which has a base formed of a combination of shallow and deep acceptors species. Specifically, elements such as Indium, Tellurium, and Gallium are deep acceptors in silicon, and are appropriate for such an application, in combination with boron as the shallow acceptor. The use of a deep acceptor for doping the base of the transistor has the benefit of providing a doping species, which increases in ionization as the temperature rises. At elevated temperatures, the fraction of, for example, indium which is ionized increases and it results in an increased Gummel number, driving down the current gain. In other words, the enhancement of the Gummel number between room temperature and an elevated temperature compensates for the increase in the ratio of collector and base currents due to band gap narrowing effects. Thus, a zero temperature coefficient bipolar transistor is provided.

公开(公告)号：US20060151842A1

公开(公告)日：2006-07-13

申请号：US11110457

申请日：2005-04-19

Applicant: Ashok Kapoor

Inventor： Ashok Kapoor

IPC: H01L21/336 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC classification number: H01L27/11 ,  G11C11/412 ,  H01L21/28052 ,  H01L29/4916 ,  H01L29/665 ,  Y10S257/903 ,  Y10S257/905 ,  Y10S257/909

Abstract: An apparatus and method for the reduction of gate leakage in deep sub-micron metal oxide semiconductor (MOS) transistors, especially useful for those used in a cross coupled static random access memory (SRAM) cell, is disclosed. In accordance with the invention, the active element of the SRAM cell is used to reduce the voltage on the gate of its transistor without impacting the switching speed of the circuit. Because the load on the output of the inverter is fixed, a reduction in the gate current is optimized to minimize the impact on the switching waveform of the memory cell. An active element formed by two materials with different Fermi potentials is used as a rectifying junction or diode. The rectifying junction also has a large parallel leakage path, which allows a finite current flow when a signal of opposite polarity is applied across this device.

Abstract translation: 公开了一种用于减少深亚微米金属氧化物半导体（MOS）晶体管中的栅极泄漏的装置和方法，特别适用于交叉耦合的静态随机存取存储器（SRAM）单元中使用的那些。 根据本发明，SRAM单元的有源元件用于降低其晶体管栅极上的电压，而不影响电路的开关速度。 由于反相器输出的负载是固定的，所以优化了栅极电流的减小以最小化对存储器单元的开关波形的影响。 由具有不同费米电位的两种材料形成的有源元件用作整流结或二极管。 整流结还具有大的并联泄漏路径，当在该器件上施加相反极性的信号时，允许有限电流流动。