Invention Application
US20060151842A1 Apparatus and method for reducing gate leakage in deep sub-micron MOS transistors using semi-rectifying contacts
失效
使用半整流触点减少深亚微米MOS晶体管栅极泄漏的装置和方法
- Patent Title: Apparatus and method for reducing gate leakage in deep sub-micron MOS transistors using semi-rectifying contacts
- Patent Title (中): 使用半整流触点减少深亚微米MOS晶体管栅极泄漏的装置和方法
-
Application No.: US11110457Application Date: 2005-04-19
-
Publication No.: US20060151842A1Publication Date: 2006-07-13
- Inventor: Ashok Kapoor
- Applicant: Ashok Kapoor
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L29/76 ; H01L29/94 ; H01L31/062 ; H01L31/113

Abstract:
An apparatus and method for the reduction of gate leakage in deep sub-micron metal oxide semiconductor (MOS) transistors, especially useful for those used in a cross coupled static random access memory (SRAM) cell, is disclosed. In accordance with the invention, the active element of the SRAM cell is used to reduce the voltage on the gate of its transistor without impacting the switching speed of the circuit. Because the load on the output of the inverter is fixed, a reduction in the gate current is optimized to minimize the impact on the switching waveform of the memory cell. An active element formed by two materials with different Fermi potentials is used as a rectifying junction or diode. The rectifying junction also has a large parallel leakage path, which allows a finite current flow when a signal of opposite polarity is applied across this device.
Public/Granted literature
Information query
IPC分类: