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    GAP PROCESSING
    1.
    发明申请
    GAP PROCESSING 有权
    GAP处理

    公开(公告)号：US20100015813A1

    公开(公告)日：2010-01-21

    申请号：US12175200

    申请日：2008-07-17

    Applicant: Arthur J. McGinnis ,  Sachin Joshi ,  Chan Lim

    Inventor： Arthur J. McGinnis ,  Sachin Joshi ,  Chan Lim

    IPC: H01L21/31

    CPC classification number: H01L21/31608 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/7682 ,  H01L21/76885

    Abstract: Among various methods, devices, and apparatuses, a number of methods are provided for forming a gap between circuitry. One such method includes depositing a first oxide precursor material on at least two conductive lines having at least one gap between the at least two conductive lines, and forming a breadloaf configuration with the first oxide precursor material on a top of each of the at least two conductive lines that leaves a space between a closest approach of at least two adjacent breadloaf configurations. The method also includes depositing a second oxide precursor material over the first oxide precursor material, where depositing the second oxide precursor material results in closing the space between the closest approach of the at least two adjacent breadloaf configurations.

    Abstract translation: 在各种方法中，设备和装置提供了用于在电路之间形成间隙的多种方法。 一种这样的方法包括在至少两条导线之间沉积第一氧化物前体材料，所述至少两条导线在至少两条导电线之间具有至少一个间隙，并且在至少两条导线中的每一条的顶部上形成具有第一氧化物前体材料的面包构型 在至少两个相邻的面包构造的最接近的方式之间留下空间的导电线。 该方法还包括在第一氧化物前体材料上沉积第二氧化物前体材料，其中沉积第二氧化物前体材料导致封闭至少两个相邻的面包构型的最接近的方式之间的空间。

    Gap processing
    2.
    发明授权
    Gap processing 有权
    差距处理

    公开(公告)号：US08058138B2

    公开(公告)日：2011-11-15

    申请号：US12175200

    申请日：2008-07-17

    Applicant: Arthur J. McGinnis ,  Sachin Joshi ,  Chan Lim

    Inventor： Arthur J. McGinnis ,  Sachin Joshi ,  Chan Lim

    IPC: H01L21/76

    CPC classification number: H01L21/31608 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/7682 ,  H01L21/76885

    Abstract: Among various methods, devices, and apparatuses, a number of methods are provided for forming a gap between circuitry. One such method includes depositing a first oxide precursor material on at least two conductive lines having at least one gap between the at least two conductive lines, and forming a breadloaf configuration with the first oxide precursor material on a top of each of the at least two conductive lines that leaves a space between a closest approach of at least two adjacent breadloaf configurations. The method also includes depositing a second oxide precursor material over the first oxide precursor material, where depositing the second oxide precursor material results in closing the space between the closest approach of the at least two adjacent breadloaf configurations.

    Abstract translation: 在各种方法中，设备和装置提供了用于在电路之间形成间隙的多种方法。 一种这样的方法包括在至少两条导线之间沉积第一氧化物前体材料，所述至少两条导线在至少两条导电线之间具有至少一个间隙，并且在至少两条导线中的每一条的顶部上形成具有第一氧化物前体材料的面包构型 在至少两个相邻的面包构造的最接近的方式之间留下空间的导电线。 该方法还包括在第一氧化物前体材料上沉积第二氧化物前体材料，其中沉积第二氧化物前体材料导致封闭至少两个相邻的面包构型的最接近的方式之间的空间。

    GAP PROCESSING
    3.
    发明申请
    GAP PROCESSING 有权
    GAP处理

    公开(公告)号：US20120040534A1

    公开(公告)日：2012-02-16

    申请号：US13282563

    申请日：2011-10-27

    Applicant: Arthur J. McGinnis ,  Sachin Joshi ,  Chan Lim

    Inventor： Arthur J. McGinnis ,  Sachin Joshi ,  Chan Lim

    IPC: H01L21/31

    CPC classification number: H01L21/31608 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/7682 ,  H01L21/76885

    Abstract: Among various methods, devices, and apparatuses, a number of methods are provided for forming a gap between circuitry. One such method includes depositing a first oxide precursor material on at least two conductive lines having at least one gap between the at least two conductive lines, and forming a breadloaf configuration with the first oxide precursor material on a top of each of the at least two conductive lines that leaves a space between a closest approach of at least two adjacent breadloaf configurations. The method also includes depositing a second oxide precursor material over the first oxide precursor material, where depositing the second oxide precursor material results in closing the space between the closest approach of the at least two adjacent breadloaf configurations.

    Abstract translation: 在各种方法中，设备和装置提供了用于在电路之间形成间隙的多种方法。 一种这样的方法包括在至少两条导线之间沉积第一氧化物前体材料，所述至少两条导线在至少两条导电线之间具有至少一个间隙，并且在至少两条导线中的每一条的顶部上形成具有第一氧化物前体材料的面包构型 在至少两个相邻的面包构造的最接近的方式之间留下空间的导电线。 该方法还包括在第一氧化物前体材料上沉积第二氧化物前体材料，其中沉积第二氧化物前体材料导致封闭至少两个相邻的面包构型的最接近的方式之间的空间。

    Gap processing
    4.
    发明授权
    Gap processing 有权
    差距处理

    公开(公告)号：US08293617B2

    公开(公告)日：2012-10-23

    申请号：US13282563

    申请日：2011-10-27

    Applicant: Arthur J. McGinnis ,  Sachin Joshi ,  Chan Lim

    Inventor： Arthur J. McGinnis ,  Sachin Joshi ,  Chan Lim

    IPC: H01L21/76

    CPC classification number: H01L21/31608 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/7682 ,  H01L21/76885

    Abstract: Among various methods, devices, and apparatuses, a number of methods are provided for forming a gap between circuitry. One such method includes depositing a first oxide precursor material on at least two conductive lines having at least one gap between the at least two conductive lines, and forming a breadloaf configuration with the first oxide precursor material on a top of each of the at least two conductive lines that leaves a space between a closest approach of at least two adjacent breadloaf configurations. The method also includes depositing a second oxide precursor material over the first oxide precursor material, where depositing the second oxide precursor material results in closing the space between the closest approach of the at least two adjacent breadloaf configurations.

    Abstract translation: 在各种方法中，设备和装置提供了用于在电路之间形成间隙的多种方法。 一种这样的方法包括在至少两条导线之间沉积第一氧化物前体材料，所述至少两条导线在至少两条导电线之间具有至少一个间隙，并且在至少两条导线中的每一条的顶部上形成具有第一氧化物前体材料的面包构型 在至少两个相邻的面包构造的最接近的方式之间留下空间的导电线。 该方法还包括在第一氧化物前体材料上沉积第二氧化物前体材料，其中沉积第二氧化物前体材料导致封闭至少两个相邻的面包构型的最接近的方式之间的空间。

    FUEL GAS CONDITIONING PROCESS USING GLASSY POLYMER MEMBRANES
    5.
    发明申请
    FUEL GAS CONDITIONING PROCESS USING GLASSY POLYMER MEMBRANES 审中-公开
    使用玻璃聚合物膜的燃料气体调节过程

    公开(公告)号：US20130014643A1

    公开(公告)日：2013-01-17

    申请号：US13182106

    申请日：2011-07-13

    Applicant: Kaaeid A. Lokhandwala ,  Maliha WIlliamson ,  Sachin Joshi

    Inventor： Kaaeid A. Lokhandwala ,  Maliha WIlliamson ,  Sachin Joshi

    IPC: B01D53/22

    CPC classification number: B01D53/228 ,  B01D2256/245 ,  B01D2257/7022 ,  C07C7/144 ,  C10L3/101 ,  C07C9/04

    Abstract: Disclosed herein is a process for conditioning natural gas containing C3+ hydrocarbons, so that it can be used as combustion fuel to run gas-powered equipment, including gas engines and turbine-driven compressors, in the gas field or the gas processing plant. The claimed process uses glassy polymeric membranes that are preferentially permeable to methane over C2+ hydrocarbons to produce a partially purified methane stream. Conditioned fuel gas has lower heating value, higher methane number, and will result in greatly reduced emissions from the engines.

    Abstract translation: 本文公开了一种用于调节含有C3 +烃的天然气的方法，使得其可以用作燃料燃料以在气田或气体处理设备中运行包括燃气发动机和涡轮驱动压缩机的气体动力设备。 所要求保护的方法使用玻璃质聚合物膜，其优先比C 2 +烃可渗透甲烷以产生部分纯化的甲烷物流。 条件燃料气体具有较低的发热量，更高的甲烷数量，并将大大减少发动机的排放。

    Comparator circuit
    6.
    发明授权
    Comparator circuit 失效
    比较器电路

    公开(公告)号：US07919991B1

    公开(公告)日：2011-04-05

    申请号：US12499771

    申请日：2009-07-08

    Applicant: Sachin Joshi

    Inventor： Sachin Joshi

    IPC: G01R29/00 ,  H03D3/00 ,  H03D9/00

    CPC classification number: H03K5/26 ,  H03K19/018528

    Abstract: A comparator circuit is disclosed that determines whether a first binary value is greater than, equal to, and/or less than a second binary value without employing binary adder circuits, and therefore is simpler, occupies less circuit area, and consumes less power than conventional comparator circuits having binary adders. For some embodiments, the comparator circuit is capable of performing full comparison operations on two or more arbitrary binary values. The comparator circuit can be implemented in TCAM devices to perform regular expression search operations.

    Abstract translation: 公开了一种比较器电路，其在不使用二进制加法器电路的情况下确定第一二进制值是否大于，等于和/或小于第二二进制值，因此更简单，占用更少的电路面积，并且消耗的功率比常规 具有二进制加法器的比较器电路。 对于一些实施例，比较器电路能够对两个或更多个任意二进制值执行完全比较操作。 比较器电路可以在TCAM设备中实现，以执行正则表达式搜索操作。

    Content addressable memory having programmable interconnect structure
    7.
    发明授权
    Content addressable memory having programmable interconnect structure 有权
    具有可编程互连结构的内容可寻址存储器

    公开(公告)号：US07643353B1

    公开(公告)日：2010-01-05

    申请号：US12131992

    申请日：2008-06-03

    Applicant: Maheshwaran Srinivasan ,  Varadarajan Srinivasan ,  Sandeep Khanna ,  Sachin Joshi ,  Mark Birman

    Inventor： Maheshwaran Srinivasan ,  Varadarajan Srinivasan ,  Sandeep Khanna ,  Sachin Joshi ,  Mark Birman

    IPC: G11C7/00

    CPC classification number: G11C15/00 ,  G11C15/04 ,  G11C15/046

    Abstract: A content addressable memory (CAM) device includes a CAM array, a programmable interconnect structure, and a priority encoder. The CAM array includes a plurality of CAM rows, each row including a number of CAM cells for storing a data word and coupled to a match line that indicates a match result for the CAM row. The programmable interconnect structure is coupled to each CAM row and is configured to selectively route the match results from a first CAM row as an input match signal to any number of arbitrarily selected CAM rows at the same time.

    Abstract translation: 内容可寻址存储器（CAM）装置包括CAM阵列，可编程互连结构和优先编码器。 CAM阵列包括多个CAM行，每行包括用于存储数据字并耦合到指示CAM行的匹配结果的匹配线的多个CAM单元。 可编程互连结构耦合到每个CAM行，并且被配置为选择性地将来自第一CAM行的匹配结果作为输入匹配信号同时路由到任意数量的任意选择的CAM行。

    Low swing dynamic circuit
    9.
    发明授权
    Low swing dynamic circuit 有权
    低摆动态电路

    公开(公告)号：US08890572B2

    公开(公告)日：2014-11-18

    申请号：US13622827

    申请日：2012-09-19

    Applicant: Sachin Joshi

    Inventor： Sachin Joshi

    IPC: H03K19/0185 ,  H03K19/096

    CPC classification number: H03K3/356156 ,  H03K3/356139 ,  H03K19/096

    Abstract: Embodiments of the present disclosure enable low swing dynamic circuits with reduced dynamic power and leakage power. In an embodiment, a level detector circuit monitors the pre-charge voltage level of the dynamic node of a dynamic circuit and discontinues the charging of the dynamic node when the pre-charge voltage exceeds a logic high reference voltage. The logic high reference voltage is selected below a supply voltage of the dynamic circuit, resulting in a low swing dynamic circuit. In another embodiment, the pull-down logic circuitry is disconnected from the dynamic node when the dynamic node voltage falls below a logic low reference voltage, above a ground voltage. In another embodiment, a DC keeper circuit of the dynamic circuit is configured based on the pre-charge level of the dynamic node.

    Abstract translation: 本公开的实施例使得具有降低的动态功率和泄漏功率的低摆动动态电路。 在一个实施例中，电平检测器电路监视动态电路的动态节点的预充电电压，并且当预充电电压超过逻辑高参考电压时，停止动态节点的充电。 逻辑高参考电压选择在动态电路的电源电压以下，导致低摆动动态电路。 在另一个实施例中，当动态节点电压低于接地电压以上的逻辑低参考电压时，下拉逻辑电路与动态节点断开连接。 在另一个实施例中，基于动态节点的预充电水平配置动态电路的直流保持器电路。

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