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    FUEL GAS CONDITIONING PROCESS USING GLASSY POLYMER MEMBRANES
    2.
    发明申请
    FUEL GAS CONDITIONING PROCESS USING GLASSY POLYMER MEMBRANES 有权
    使用玻璃聚合物膜的燃料气体调节过程

    公开(公告)号：US20140107388A1

    公开(公告)日：2014-04-17

    申请号：US14132655

    申请日：2013-12-18

    申请人： Kaaeid A. Lokhandwala ,  Maliha Williamson ,  Sachin Joshi

    发明人： Kaaeid A. Lokhandwala ,  Maliha Williamson ,  Sachin Joshi

    IPC分类号： C07C7/144

    CPC分类号： C07C7/144 ,  B01D53/228 ,  B01D2256/245 ,  B01D2257/7022 ,  C10L3/101 ,  C07C9/04

    摘要： Disclosed herein is a process for conditioning natural gas containing C3+ hydrocarbons, so that it can be used as combustion fuel to run gas-powered equipment, including gas engines and turbine-driven compressors, in the gas field or the gas processing plant. The claimed process use glassy polymeric membranes that are preferentially permeable to methane over C2+ hydrocarbons to produce a partially purified methane stream. The process operates at a stage cut of at least about 5%.

    摘要翻译： 本文公开了一种用于调节含有C3 +烃的天然气的方法，使得其可以用作燃料燃料以在气田或气体处理设备中运行包括燃气发动机和涡轮驱动压缩机的气体动力设备。 所要求保护的方法使用玻璃质聚合物膜，其优先通过甲烷超过C 2 +烃以产生部分纯化的甲烷流。 该过程在至少约5％的阶段切割操作。

    GAP PROCESSING
    3.
    发明申请
    GAP PROCESSING 有权
    GAP处理

    公开(公告)号：US20120040534A1

    公开(公告)日：2012-02-16

    申请号：US13282563

    申请日：2011-10-27

    申请人： Arthur J. McGinnis ,  Sachin Joshi ,  Chan Lim

    发明人： Arthur J. McGinnis ,  Sachin Joshi ,  Chan Lim

    IPC分类号： H01L21/31

    CPC分类号： H01L21/31608 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/7682 ,  H01L21/76885

    摘要： Among various methods, devices, and apparatuses, a number of methods are provided for forming a gap between circuitry. One such method includes depositing a first oxide precursor material on at least two conductive lines having at least one gap between the at least two conductive lines, and forming a breadloaf configuration with the first oxide precursor material on a top of each of the at least two conductive lines that leaves a space between a closest approach of at least two adjacent breadloaf configurations. The method also includes depositing a second oxide precursor material over the first oxide precursor material, where depositing the second oxide precursor material results in closing the space between the closest approach of the at least two adjacent breadloaf configurations.

    摘要翻译： 在各种方法中，设备和装置提供了用于在电路之间形成间隙的多种方法。 一种这样的方法包括在至少两条导线之间沉积第一氧化物前体材料，所述至少两条导线在至少两条导电线之间具有至少一个间隙，并且在至少两条导线中的每一条的顶部上形成具有第一氧化物前体材料的面包构型 在至少两个相邻的面包构造的最接近的方式之间留下空间的导电线。 该方法还包括在第一氧化物前体材料上沉积第二氧化物前体材料，其中沉积第二氧化物前体材料导致封闭至少两个相邻的面包构型的最接近的方式之间的空间。

    Content addressable memory having selectively interconnected rows of counter circuits
    4.
    发明授权
    Content addressable memory having selectively interconnected rows of counter circuits 有权
    具有有选择地互连的计数器电路行的内容寻址存储器

    公开(公告)号：US07876590B2

    公开(公告)日：2011-01-25

    申请号：US12873183

    申请日：2010-08-31

    申请人： Sachin Joshi ,  Mark Birman ,  Maheshwaran Srinivasan ,  Sandeep Khanna ,  Varadarajan Srinivasan

    发明人： Sachin Joshi ,  Mark Birman ,  Maheshwaran Srinivasan ,  Sandeep Khanna ,  Varadarajan Srinivasan

    IPC分类号： G11C15/00

    CPC分类号： G11C15/00 ,  G11C15/04 ,  G11C15/046

    摘要： A content addressable memory (CAM) device includes a plurality of CAM rows, a number of sequencing logic circuits, and a programmable interconnect structure. Each CAM row includes a number of CAM cells to generate a match signal on a match line and includes an enable input. Each sequencing logic circuit includes an input and an output, and is configured to count sequences of match signals from the CAM rows. The programmable interconnect structure selectively connects the match line of any CAM row to the input of any sequencing logic circuit, and selectively connects the output of any sequencing logic circuit to the enable input of any CAM row.

    摘要翻译： 内容可寻址存储器（CAM）设备包括多个CAM行，多个排序逻辑电路和可编程互连结构。 每个CAM行包括多个CAM单元，以在匹配线上生成匹配信号并且包括使能输入。 每个排序逻辑电路包括输入和输出，并且被配置为对来自CAM行的匹配信号的序列进行计数。 可编程互连结构选择性地将任何CAM行的匹配线连接到任何排序逻辑电路的输入，并且将任何排序逻辑电路的输出选择性地连接到任何CAM行的使能输入。

    Content addresable memory having selectively interconnected counter circuits
    5.
    发明授权
    Content addresable memory having selectively interconnected counter circuits 有权
    具有选择性地互连的计数器电路的内容可存储存储器

    公开(公告)号：US07826242B2

    公开(公告)日：2010-11-02

    申请号：US12619607

    申请日：2009-11-16

    申请人： Sachin Joshi ,  Mark Birman ,  Maheshwaran Srinivasan ,  Sandeep Khanna ,  Varadarajan Srinivasan

    发明人： Sachin Joshi ,  Mark Birman ,  Maheshwaran Srinivasan ,  Sandeep Khanna ,  Varadarajan Srinivasan

    IPC分类号： G11C15/00

    CPC分类号： G11C15/00 ,  G11C15/04 ,  G11C15/046

    摘要： A content addressable memory (CAM) device includes a plurality of CAM rows, a number of sequencing logic circuits, and a programmable interconnect structure. Each CAM row includes a number of CAM cells to generate a match signal on a match line and includes an enable input. Each sequencing logic circuit includes an input and an output, and is configured to count sequences of match signals from the CAM rows. The programmable interconnect structure selectively connects the match line of any CAM row to the input of any sequencing logic circuit, and selectively connects the output of any sequencing logic circuit to the enable input of any CAM row.

    摘要翻译： 内容可寻址存储器（CAM）设备包括多个CAM行，多个排序逻辑电路和可编程互连结构。 每个CAM行包括多个CAM单元，以在匹配线上生成匹配信号并且包括使能输入。 每个排序逻辑电路包括输入和输出，并且被配置为对来自CAM行的匹配信号的序列进行计数。 可编程互连结构选择性地将任何CAM行的匹配线连接到任何排序逻辑电路的输入，并且将任何排序逻辑电路的输出选择性地连接到任何CAM行的使能输入。

    Content addresable memory having programmable interconnect structure
    6.
    发明授权
    Content addresable memory having programmable interconnect structure 有权
    具有可编程互连结构的内容可存储存储器

    公开(公告)号：US07821844B2

    公开(公告)日：2010-10-26

    申请号：US12617369

    申请日：2009-11-12

    申请人： Maheshwaran Srinivasan ,  Varadarajan Srinivasan ,  Sandeep Khanna ,  Sachin Joshi ,  Mark Birman

    发明人： Maheshwaran Srinivasan ,  Varadarajan Srinivasan ,  Sandeep Khanna ,  Sachin Joshi ,  Mark Birman

    IPC分类号： G11C7/00

    CPC分类号： G11C15/00 ,  G11C15/04 ,  G11C15/046

    摘要： A content addressable memory (CAM) device includes a CAM array, a programmable interconnect structure, and a priority encoder. The CAM array includes a plurality of CAM rows, each row including a number of CAM cells for storing a data word and coupled to a match line that indicates a match result for the CAM row. The programmable interconnect structure is coupled to each CAM row and a plurality of CAM rows, each row including a number of CAM cells for storing a data word and coupled to a match line that indicates match results for the row. The programmable interconnect structure coupled to each CAM row, and is configured to logically connect any number N of selected CAM rows together to form a data word chain spanning N rows, regardless of whether the selected CAM rows are contiguous.

    摘要翻译： 内容可寻址存储器（CAM）装置包括CAM阵列，可编程互连结构和优先编码器。 CAM阵列包括多个CAM行，每行包括用于存储数据字并耦合到指示CAM行的匹配结果的匹配线的多个CAM单元。 可编程互连结构耦合到每个CAM行和多个CAM行，每行包括用于存储数据字并耦合到指示行的匹配结果的匹配线的多个CAM单元。 可编程互连结构耦合到每个CAM行，并且被配置为将任何数目N个所选择的CAM行逻辑地连接在一起，以形成横跨N行的数据字链，而不管所选择的CAM行是否是连续的。

    CONTENT ADDRESABLE MEMORY HAVING SELECTIVELY INTERCONNECTED COUNTER CIRCUITS
    7.
    发明申请
    CONTENT ADDRESABLE MEMORY HAVING SELECTIVELY INTERCONNECTED COUNTER CIRCUITS 有权
    内容可选存储器，具有选择性的互连计数器电路

    公开(公告)号：US20100054013A1

    公开(公告)日：2010-03-04

    申请号：US12619607

    申请日：2009-11-16

    申请人： Sachin Joshi ,  Mark Birman ,  Maheshwaran Srinivasan ,  Sandeep Khanna ,  Varadarajan Srinivasan

    发明人： Sachin Joshi ,  Mark Birman ,  Maheshwaran Srinivasan ,  Sandeep Khanna ,  Varadarajan Srinivasan

    IPC分类号： G11C15/00 ,  G11C8/00

    CPC分类号： G11C15/00 ,  G11C15/04 ,  G11C15/046

    摘要： A content addressable memory (CAM) device includes a plurality of CAM rows, a number of sequencing logic circuits, and a programmable interconnect structure. Each CAM row includes a number of CAM cells to generate a match signal on a match line and includes an enable input. Each sequencing logic circuit includes an input and an output, and is configured to count sequences of match signals from the CAM rows. The programmable interconnect structure selectively connects the match line of any CAM row to the input of any sequencing logic circuit, and selectively connects the output of any sequencing logic circuit to the enable input of any CAM row.

    摘要翻译： 内容可寻址存储器（CAM）设备包括多个CAM行，多个排序逻辑电路和可编程互连结构。 每个CAM行包括多个CAM单元，以在匹配线上生成匹配信号并且包括使能输入。 每个排序逻辑电路包括输入和输出，并且被配置为对来自CAM行的匹配信号的序列进行计数。 可编程互连结构选择性地将任何CAM行的匹配线连接到任何排序逻辑电路的输入，并且将任何排序逻辑电路的输出选择性地连接到任何CAM行的使能输入。

    CONTENT ADDRESABLE MEMORY HAVING PROGRAMMABLE INTERCONNECT STRUCTURE
    8.
    发明申请
    CONTENT ADDRESABLE MEMORY HAVING PROGRAMMABLE INTERCONNECT STRUCTURE 有权
    内容可编程存储器具有可编程互连结构

    公开(公告)号：US20100054012A1

    公开(公告)日：2010-03-04

    申请号：US12617369

    申请日：2009-11-12

    申请人： Maheshwaran Srinivasan ,  Varadarajan Srinivasan ,  Sandeep Khanna ,  Sachin Joshi ,  Mark Birman

    发明人： Maheshwaran Srinivasan ,  Varadarajan Srinivasan ,  Sandeep Khanna ,  Sachin Joshi ,  Mark Birman

    IPC分类号： G11C15/00 ,  G11C7/00 ,  G11C5/14

    CPC分类号： G11C15/00 ,  G11C15/04 ,  G11C15/046

    摘要： A content addressable memory (CAM) device includes a CAM array, a programmable interconnect structure, and a priority encoder. The CAM array includes a plurality of CAM rows, each row including a number of CAM cells for storing a data word and coupled to a match line that indicates a match result for the CAM row. The programmable interconnect structure is coupled to each CAM row and a plurality of CAM rows, each row including a number of CAM cells for storing a data word and coupled to a match line that indicates match results for the row. The programmable interconnect structure coupled to each CAM row, and is configured to logically connect any number N of selected CAM rows together to form a data word chain spanning N rows, regardless of whether the selected CAM rows are contiguous.

    摘要翻译： 内容可寻址存储器（CAM）装置包括CAM阵列，可编程互连结构和优先编码器。 CAM阵列包括多个CAM行，每行包括用于存储数据字并耦合到指示CAM行的匹配结果的匹配线的多个CAM单元。 可编程互连结构耦合到每个CAM行和多个CAM行，每行包括用于存储数据字并耦合到指示行的匹配结果的匹配线的多个CAM单元。 可编程互连结构耦合到每个CAM行，并且被配置为将任何数目N个所选择的CAM行逻辑地连接在一起，以形成横跨N行的数据字链，而不管所选择的CAM行是否是连续的。

    FUEL GAS CONDITIONING PROCESS USING GLASSY POLYMER MEMBRANES
    9.
    发明申请
    FUEL GAS CONDITIONING PROCESS USING GLASSY POLYMER MEMBRANES 审中-公开
    使用玻璃聚合物膜的燃料气体调节过程

    公开(公告)号：US20130014643A1

    公开(公告)日：2013-01-17

    申请号：US13182106

    申请日：2011-07-13

    申请人： Kaaeid A. Lokhandwala ,  Maliha WIlliamson ,  Sachin Joshi

    发明人： Kaaeid A. Lokhandwala ,  Maliha WIlliamson ,  Sachin Joshi

    IPC分类号： B01D53/22

    CPC分类号： B01D53/228 ,  B01D2256/245 ,  B01D2257/7022 ,  C07C7/144 ,  C10L3/101 ,  C07C9/04

    摘要： Disclosed herein is a process for conditioning natural gas containing C3+ hydrocarbons, so that it can be used as combustion fuel to run gas-powered equipment, including gas engines and turbine-driven compressors, in the gas field or the gas processing plant. The claimed process uses glassy polymeric membranes that are preferentially permeable to methane over C2+ hydrocarbons to produce a partially purified methane stream. Conditioned fuel gas has lower heating value, higher methane number, and will result in greatly reduced emissions from the engines.

    摘要翻译： 本文公开了一种用于调节含有C3 +烃的天然气的方法，使得其可以用作燃料燃料以在气田或气体处理设备中运行包括燃气发动机和涡轮驱动压缩机的气体动力设备。 所要求保护的方法使用玻璃质聚合物膜，其优先比C 2 +烃可渗透甲烷以产生部分纯化的甲烷物流。 条件燃料气体具有较低的发热量，更高的甲烷数量，并将大大减少发动机的排放。

    Comparator circuit
    10.
    发明授权
    Comparator circuit 失效
    比较器电路

    公开(公告)号：US07919991B1

    公开(公告)日：2011-04-05

    申请号：US12499771

    申请日：2009-07-08

    申请人： Sachin Joshi

    发明人： Sachin Joshi

    IPC分类号： G01R29/00 ,  H03D3/00 ,  H03D9/00

    CPC分类号： H03K5/26 ,  H03K19/018528

    摘要： A comparator circuit is disclosed that determines whether a first binary value is greater than, equal to, and/or less than a second binary value without employing binary adder circuits, and therefore is simpler, occupies less circuit area, and consumes less power than conventional comparator circuits having binary adders. For some embodiments, the comparator circuit is capable of performing full comparison operations on two or more arbitrary binary values. The comparator circuit can be implemented in TCAM devices to perform regular expression search operations.

    摘要翻译： 公开了一种比较器电路，其在不使用二进制加法器电路的情况下确定第一二进制值是否大于，等于和/或小于第二二进制值，因此更简单，占用更少的电路面积，并且消耗的功率比常规 具有二进制加法器的比较器电路。 对于一些实施例，比较器电路能够对两个或更多个任意二进制值执行完全比较操作。 比较器电路可以在TCAM设备中实现，以执行正则表达式搜索操作。