Adaptive timeout mechanism
    1.
    发明授权

    公开(公告)号:US11048569B1

    公开(公告)日:2021-06-29

    申请号:US16794467

    申请日:2020-02-19

    摘要: Disclosed herein are techniques for preventing or minimizing completion timeout errors on a computer device. An apparatus include a processing logic circuit and a timeout logic. The timeout logic is configured to: generate a timeout event based on a transaction not completed by the processing logic circuit within a timeout period; determine a number of the timeout events generated during a monitoring period; and responsive to determining that the number equals to or exceeds a threshold, reduce the timeout period.

    Adaptive use of search modes based on bandwidth availability

    公开(公告)号:US10694189B1

    公开(公告)日:2020-06-23

    申请号:US16357120

    申请日:2019-03-18

    摘要: Reference data is one type of data that the video accelerator may frequently be read from external memory. In various examples, the video accelerator can adaptively select inter-prediction modes based on the bandwidth to external memory that is available at any point in time. The video accelerator can determine the amount of bandwidth that is available, and when the bandwidth is insufficient for obtaining reference data for all possible inter-prediction modes, the video accelerator can select an inter-prediction mode based on the size of the reference window associated with the inter-prediction mode, the size being within an amount of data that can be read with the available bandwidth. The video accelerator can then obtain a reference window from external memory, and perform prediction using the selected inter-prediction mode and the reference window.

    Detection of errors in a ternary content addressable memory

    公开(公告)号:US10243590B1

    公开(公告)日:2019-03-26

    申请号:US14857787

    申请日:2015-09-17

    IPC分类号: H03M13/29 G11C15/00 G06F11/10

    摘要: A ternary content addressable memory (TCAM) may implement complete detection of single and double bit errors for entries. A single error correction double error detection (SECDED) error correction code may be generated and maintained for each entry in the TCAM. The SECDED error correction code may be generated from the parity bit and bits that indicate don't−care conditions in memory cells storing a value for an entry in the TCAM. When an entry of the TCAM is accessed, the value of the entry may be validated with respect to the SECDED error correction code. All single bit errors and double bit errors in the value or data stored for the value, such as a parity bit or value bit, may be detected. All single bit errors and some double bit errors may be corrected.

    PROGRAMMABLE TUNNEL CREATION FOR HARDWARE-BASED PACKET PROCESSING

    公开(公告)号:US20180367338A1

    公开(公告)日:2018-12-20

    申请号:US16049667

    申请日:2018-07-30

    摘要: A packet processor may implement programmable tunnel creation. A network packet may be received at a packet processor. A tunneling protocol may be identified for the network packet. The packet processor may access one or more memories to obtain tunnel header data that includes a tunnel header and field identifiers which indicate respective fields in the tunnel header that are determined based on data in the network packet. The tunnel header data may have been stored in the one or more memories prior to receiving the network packet. The network packet may be modified to insert the tunnel header into the network packet including the respective fields indicated by the field identifiers. The modified packet may then be transmitted.

    Reconfiguring programmable hardware when a virtual machine is active

    公开(公告)号:US10776142B1

    公开(公告)日:2020-09-15

    申请号:US15840807

    申请日:2017-12-13

    摘要: Disclosed herein are techniques for configuring a shell logic in a configurable computing system while a client virtual machine (VM) using the shell logic is active. In certain embodiments, a configurable device includes a client configurable circuit associated with a client virtual machine, and a shell logic configured to isolate the client configurable circuit. The shell logic includes a reconfigurable shell, an isolation logic, and a packet processing logic. The isolation logic is configured to disable communication between the reconfigurable shell and the client virtual machine when the reconfigurable shell is being reconfigured. The packet processing logic is configured to service transactions between the client virtual machine and the configurable device after the communication between the reconfigurable shell and the client virtual machine is disabled. In some embodiments, the shell logic also includes a mailbox configured to enable communication between the client virtual machine and a management virtual machine.

    Programmable tunnel creation for hardware-based packet processing

    公开(公告)号:US10673650B2

    公开(公告)日:2020-06-02

    申请号:US16049667

    申请日:2018-07-30

    摘要: A packet processor may implement programmable tunnel creation. A network packet may be received at a packet processor. A tunneling protocol may be identified for the network packet. The packet processor may access one or more memories to obtain tunnel header data that includes a tunnel header and field identifiers which indicate respective fields in the tunnel header that are determined based on data in the network packet. The tunnel header data may have been stored in the one or more memories prior to receiving the network packet. The network packet may be modified to insert the tunnel header into the network packet including the respective fields indicated by the field identifiers. The modified packet may then be transmitted.