知搜-全球专利检索

  1. 登录
  2. 注册

搜索结果

7 条记录 (耗时 0.021 秒)

    Method and system for temperature cycling at an interface between an IC die and an underfill material
    2.
    发明授权
    Method and system for temperature cycling at an interface between an IC die and an underfill material 失效
    在IC模具和底部填充材料之间的界面处的温度循环的方法和系统

    公开(公告)号：US06821796B1

    公开(公告)日：2004-11-23

    申请号：US10199237

    申请日：2002-07-19

    申请人： Zhihong Mai ,  Jiann Min Chin ,  Lihong Cao

    发明人： Zhihong Mai ,  Jiann Min Chin ,  Lihong Cao

    IPC分类号： H01L2166

    CPC分类号： G01N3/60 ,  G01N2033/0095 ,  G01N2203/005 ,  G01N2203/0057

    摘要： For temperature cycling at a material of an IC (integrated circuit) package, a laser beam is directed to the material such that the material absorbs the laser beam to become heated. A laser controller adjusts at least one property of the laser beam until the temperature of the material reaches a predetermined high-end temperature. The present invention may be used for a flip-chip IC package with the laser beam being directed toward a back-side of an IC die that is exposed on the IC package. In that case, the laser beam is comprised of light having a wavelength that is within a transmission region of a semiconductor material of the IC die such that the laser beam reaches the material on the front side of the IC die.

    摘要翻译： 对于IC（集成电路）封装的材料的温度循环，激光束被引导到材料，使得材料吸收激光束以加热。 激光控制器调节激光束的至少一个特性，直到材料的温度达到预定的高端温度。 本发明可以用于倒装芯片IC封装，其中激光束指向暴露在IC封装上的IC芯片的背面。 在这种情况下，激光束由具有在IC芯片的半导体材料的透射区域内的波长的光构成，使得激光束到达IC芯片前侧的材料。

    Method of and apparatus for testing an integrated circuit package
    3.
    发明授权
    Method of and apparatus for testing an integrated circuit package 失效
    用于测试集成电路封装的方法和装置

    公开(公告)号：US06531865B1

    公开(公告)日：2003-03-11

    申请号：US09741626

    申请日：2000-12-19

    申请人： Zhihong Mai ,  Seok Hiong Tan ,  Seck June Foo

    发明人： Zhihong Mai ,  Seok Hiong Tan ,  Seck June Foo

    IPC分类号： G01R3128

    CPC分类号： G01R31/2831 ,  G01R31/2853

    摘要： A test circuit for and method of testing integrated circuit packages can be utilized to determine the existence of one or more short circuits between adjacent connectors. The system includes an interface configured to electrically connect the conductors of the integrated circuit package. The interface groups the conductors into a plurality of nodes. The number of nodes is no more than one-half the number of conductors. A control circuit is coupled to the interface. The control circuit determines the existence of one or more short circuits between adjacent conductors in response to signals on the nodes.

    摘要翻译： 可以使用用于测试集成电路封装的测试电路和方法来确定相邻连接器之间的一个或多个短路的存在。 该系统包括被配置为电连接集成电路封装的导体的接口。 接口将导体分成多个节点。 节点数量不超过导体数量的一半。 控制电路耦合到接口。 响应于节点上的信号，控制电路确定相邻导体之间的一个或多个短路的存在。

    Method and system for introducing physical damage into an integrated circuit device for verifying testing program and its results
    4.
    发明申请
    Method and system for introducing physical damage into an integrated circuit device for verifying testing program and its results 有权
    将物理损伤引入集成电路设备的方法和系统，以验证测试程序及其结果

    公开(公告)号：US20120086468A1

    公开(公告)日：2012-04-12

    申请号：US12925031

    申请日：2010-10-12

    申请人： Zhihong Mai ,  Pik Kee Tan ,  Guo Chang Man ,  Jeffrey Lam ,  Liang Choo Hsia

    发明人： Zhihong Mai ,  Pik Kee Tan ,  Guo Chang Man ,  Jeffrey Lam ,  Liang Choo Hsia

    IPC分类号： H03K19/003

    CPC分类号： G01R31/311 ,  G01R31/001 ,  G01R31/318511

    摘要： According to an embodiment of the disclosure, a method verifies bitmap information or test data information for a semiconductor device. The method places a defect on a semiconductor device at an actual defect location using a laser to physically damage the semiconductor device. A logical address associated with the defect is detected and bitmap information or test data information is reviewed to determine an expected location corresponding to the logical address. Then, the accuracy of the bitmap information or the test data information is determined by comparing the actual defect location with the expected location. A deviation between the two indicates an inaccuracy.

    摘要翻译： 根据本公开的实施例，一种方法验证半导体器件的位图信息或测试数据信息。 该方法使用激光将实际缺陷位置的缺陷放置在半导体器件上以物理地损坏半导体器件。 检测与缺陷相关联的逻辑地址，并且对位图信息或测试数据信息进行检查以确定对应于逻辑地址的期望位置。 然后，通过将实际缺陷位置与预期位置进行比较来确定位图信息或测试数据信息的准确度。 两者之间的偏差表示不准确。

    Method and system for introducing physical damage into an integrated circuit device for verifying testing program and its results
    6.
    发明授权
    Method and system for introducing physical damage into an integrated circuit device for verifying testing program and its results 有权
    将物理损伤引入集成电路设备的方法和系统，以验证测试程序及其结果

    公开(公告)号：US08489945B2

    公开(公告)日：2013-07-16

    申请号：US12925031

    申请日：2010-10-12

    申请人： Zhihong Mai ,  Pik Kee Tan ,  Guo Chang Man ,  Jeffrey Lam ,  Liang Choo Hsia

    发明人： Zhihong Mai ,  Pik Kee Tan ,  Guo Chang Man ,  Jeffrey Lam ,  Liang Choo Hsia

    IPC分类号： G11C29/00

    CPC分类号： G01R31/311 ,  G01R31/001 ,  G01R31/318511

    摘要： According to an embodiment of the disclosure, a method verifies bitmap information or test data information for a semiconductor device. The method places a defect on a semiconductor device at an actual defect location using a laser to physically damage the semiconductor device. A logical address associated with the defect is detected and bitmap information or test data information is reviewed to determine an expected location corresponding to the logical address. Then, the accuracy of the bitmap information or the test data information is determined by comparing the actual defect location with the expected location. A deviation between the two indicates an inaccuracy.

    摘要翻译： 根据本公开的实施例，一种方法验证半导体器件的位图信息或测试数据信息。 该方法使用激光将实际缺陷位置的缺陷放置在半导体器件上以物理地损坏半导体器件。 检测与缺陷相关联的逻辑地址，并且对位图信息或测试数据信息进行检查以确定对应于逻辑地址的期望位置。 然后，通过将实际缺陷位置与预期位置进行比较来确定位图信息或测试数据信息的准确度。 两者之间的偏差表示不准确。