公开(公告)号：US20130009313A1

公开(公告)日：2013-01-10

申请号：US13433061

申请日：2012-03-28

申请人： Po-Shing Chiang ,  Ping-Cheng Hu ,  Yu-Fang Tsai

发明人： Po-Shing Chiang ,  Ping-Cheng Hu ,  Yu-Fang Tsai

IPC分类号： H01L23/48 ,  H01L21/60

CPC分类号： H01L23/488 ,  H01L21/4832 ,  H01L21/56 ,  H01L23/49541 ,  H01L23/49582 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00012

摘要： A semiconductor device package including a substrate, first and second solder joints, a die pad, leads and enhancement elements surrounding the die pad, a chip electrically connected to the leads, and a package body encapsulating the chip, portions of the leads, and portions of the enhancement elements, but leaving exposed at least a side surface of each enhancement element. Side surfaces of the enhancement elements and the package body are coplanar. The substrate includes first pads corresponding to the leads and second pads corresponding to the enhancement elements. The first solder joints are disposed between the first pads and the leads. The second solder joints are disposed between the second pads and the enhancement elements. The second solder joints contact side surfaces of the enhancement elements. The surface area of the second pads is greater than the surface area of the corresponding enhancement elements.

摘要翻译： 一种半导体器件封装，包括基板，第一和第二焊点，芯片焊盘，引线和围绕芯片焊盘的增强元件，与引线电连接的芯片以及封装芯片，引线部分和部分 的增强元件，但是留下每个增强元件的至少一个侧表面。 增强元件和封装主体的侧表面是共面的。 衬底包括对应于引线的第一焊盘和对应于增强元件的第二焊盘。 第一焊点设置在第一焊盘和引线之间。 第二焊点设置在第二焊盘和增强元件之间。 第二焊点接触增强元件的侧表面。 第二焊盘的表面积大于相应增强元件的表面积。

公开(公告)号：US07037750B2

公开(公告)日：2006-05-02

申请号：US10776490

申请日：2004-02-11

申请人： Yu-Fang Tsai ,  Chin-Hsien Lin ,  Tsung-Yueh Tsai

发明人： Yu-Fang Tsai ,  Chin-Hsien Lin ,  Tsung-Yueh Tsai

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L24/32 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/36 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/32188 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

摘要： A method of manufacturing a package is disclosed. The manufacturing method includes the steps of providing a substrate having an opening, disposing a metal slice on a bottom surface of the substrate to cover the opening and bond pads on the bottom surface of the substrate, disposing a die on the metal slice inside the opening or above the top surface of the substrate outside the opening, forming a number of bond wires between the top surface of the die and the top surface of the substrate to electrically connect the die to the substrate, forming an encapsulating mold compound to cover the die, the bond wires, and a part of the top surface of the substrate, removing a part of the metal slice to form a metal heat slug thermally connected to the die and to expose the bond pads, and forming a number of solder balls on the exposed bond pads.

摘要翻译： 公开了制造封装的方法。 该制造方法包括以下步骤：提供具有开口的基板，在基板的底表面上设置金属切片以覆盖基板的底表面上的开口和接合焊盘;将金属模设置在开口内的金属切片上 或在开口外部的基板的顶表面上方，在模具的顶表面和基板的顶表面之间形成多个接合线，以将模具电连接到基板，形成封装模具化合物以覆盖模具 键合线和衬底的顶表面的一部分，去除金属片的一部分以形成热连接到管芯的金属加热片，并露出接合焊盘，并在其上形成多个焊球 暴露的焊盘。

公开(公告)号：US07026709B2

公开(公告)日：2006-04-11

申请号：US10711575

申请日：2004-09-25

申请人： Yu-Fang Tsai ,  Jung-Kun Kang ,  Tsung-Yueh Tsai

发明人： Yu-Fang Tsai ,  Jung-Kun Kang ,  Tsung-Yueh Tsai

IPC分类号： H01L23/02 ,  H01L23/34 ,  H01L29/40 ,  H01L23/12 ,  H01L23/29

CPC分类号： H01L24/73 ,  H01L23/3128 ,  H01L23/4334 ,  H01L24/45 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/8592 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00014 ,  H01L2924/00

摘要： A stacked chip-packaging structure consisting of a plurality of chip-packaging units is provided. Each of the chip-packaging units includes a substrate, a chip, a plurality of wires, a molding compound, and a plurality of solder balls. The chip-packaging units are, for example, of a BGA structure with high pin count, and are stacked up one over another and electrically connected through solder balls. With such structural features, the space that the stacked chip-packaging structure occupies is reduced and consequently the entire structure can be miniaturized.

摘要翻译： 提供由多个芯片封装单元组成的堆叠式芯片封装结构。 每个芯片封装单元包括基板，芯片，多根电线，模塑料和多个焊球。 芯片封装单元例如是具有高引脚数的BGA结构，并且一个接一个堆叠并通过焊球电连接。 利用这种结构特征，堆叠的芯片封装结构占据的空间减小，因此整个结构可以小型化。

公开(公告)号：US20050139979A1

公开(公告)日：2005-06-30

申请号：US11026763

申请日：2004-12-31

申请人： Su Tao ,  Yu-Fang Tsai

发明人： Su Tao ,  Yu-Fang Tsai

IPC分类号： H01L23/02 ,  H01L23/31 ,  H01L23/433 ,  H01L23/48 ,  H01L25/065 ,  H01L25/10

CPC分类号： H01L25/03 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/4334 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The present invention relates to a multi-chip package structure, comprising a first substrate, a first chip, a sub-package and a first molding compound. The first chip is attached to the first substrate. The first molding compound encapsulates the first chip, the sub-package and the top surface of the first substrate. The bottom surface of the sub-package is attached to the first chip. The sub-package comprises a second substrate, a second chip and a second molding compound. The second substrate has a top surface and a bottom surface, and is electrically connected to the first chip. The second chip is attached to the top surface of the second substrate to which the second chip is electrically connected. The second molding compound encapsulates the second chip and part of the top surface of the second substrate. Whereby, the relative large area caused by the parallel arrangement of a plurality of conventional package structures can be reduced, and there is no need to redesign signal-transmitting path.

摘要翻译： 本发明涉及一种多芯片封装结构，包括第一基板，第一芯片，子封装和第一模塑料。 第一芯片附接到第一基板。 第一模塑料封装第一芯片，子封装和第一衬底的顶表面。 子封装的底表面附接到第一芯片。 该子组件包括第二衬底，第二芯片和第二模塑料。 第二基板具有顶表面和底表面，并且电连接到第一芯片。 第二芯片附接到第二芯片电连接到的第二基板的顶表面。 第二模塑料包封第二芯片和第二基板顶表面的一部分。 由此，可以减少由多个常规封装结构的平行布置引起的相对大的面积，并且不需要重新设计信号传输路径。

公开(公告)号：US06176417B1

公开(公告)日：2001-01-23

申请号：US09419288

申请日：1999-10-15

申请人： Yu-Fang Tsai ,  Su Tao ,  Simon Lee ,  Tao Yu Chen

发明人： Yu-Fang Tsai ,  Su Tao ,  Simon Lee ,  Tao Yu Chen

IPC分类号： B23K3100

CPC分类号： H01L24/85 ,  B23K20/007 ,  H01L24/03 ,  H01L24/05 ,  H01L24/48 ,  H01L24/78 ,  H01L2224/03 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/4851 ,  H01L2224/48511 ,  H01L2224/78301 ,  H01L2224/7855 ,  H01L2224/85051 ,  H01L2224/85186 ,  H01L2224/85201 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85399 ,  H01L2224/85986 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/00011 ,  H01L2224/13099 ,  H01L2224/45099 ,  H01L2924/00

摘要： A ball bonding method on a chip mainly comprises steps of: a wire is burned to form a ball on a capillary; the capillary is moved down to a second bonding point for ball bonding; and the capillary is moved up in a vertical direction thereby pulling the tip of the ball to be cut such that the ball has a uniformly body shape and tip height. Therefore, the ball provides uniform body shape and tip height for wire bonding at a second bonding point under lower variability conditions thus increasing the reliability of products.

摘要翻译： 芯片上的球焊方法主要包括以下步骤：将线烧成毛细管上的球; 毛细管向下移动到用于球接合的第二接合点; 并且毛细管沿垂直方向向上移动，从而拉动要切割的球的尖端，使得球具有均匀的体形和尖端高度。 因此，球在较低变异条件下，在第二接合点提供均匀的体形和尖端高度用于引线接合，从而增加产品的可靠性。

公开(公告)号：US20130241041A1

公开(公告)日：2013-09-19

申请号：US13421570

申请日：2012-03-15

申请人： Lin-Wang Yu ,  Ping-Cheng Hu ,  Che-Chin Chang ,  Yu-Fang Tsai

发明人： Lin-Wang Yu ,  Ping-Cheng Hu ,  Che-Chin Chang ,  Yu-Fang Tsai

IPC分类号： H01L23/495 ,  H01L21/60

CPC分类号： H01L24/97 ,  H01L21/4832 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49579 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/78 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/2919 ,  H01L2224/29294 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/78251 ,  H01L2224/83447 ,  H01L2224/8346 ,  H01L2224/8385 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/85464 ,  H01L2224/85805 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2224/45099

摘要： A semiconductor package with a die pad, a die disposed on the die pad, and a first lead disposed about the die pad. The first lead includes a contact element, an extension element extending substantially in the direction of the die pad, and a concave surface disposed between the contact element and the extension element. A second lead having a concave surface is also disposed about the die pad. The first lead concave surface is opposite in direction to the second lead concave surface.

摘要翻译： 具有管芯焊盘的半导体封装，设置在管芯焊盘上的管芯和围绕管芯焊盘设置的第一引线。 第一引线包括接触元件，基本上沿芯片焊盘的方向延伸的延伸元件，以及设置在接触元件和延伸元件之间的凹表面。 具有凹面的第二引线也围绕芯片焊盘设置。 第一引线凹面与第二引线凹面的方向相反。

公开(公告)号：US08502363B2

公开(公告)日：2013-08-06

申请号：US13433061

申请日：2012-03-28

申请人： Po-Shing Chiang ,  Ping-Cheng Hu ,  Yu-Fang Tsai

发明人： Po-Shing Chiang ,  Ping-Cheng Hu ,  Yu-Fang Tsai

IPC分类号： H01L23/495 ,  H01L21/00 ,  H01R9/00

CPC分类号： H01L23/488 ,  H01L21/4832 ,  H01L21/56 ,  H01L23/49541 ,  H01L23/49582 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00012

摘要： A semiconductor device package including a substrate, first and second solder joints, a die pad, leads and enhancement elements surrounding the die pad, a chip electrically connected to the leads, and a package body encapsulating the chip, portions of the leads, and portions of the enhancement elements, but leaving exposed at least a side surface of each enhancement element. Side surfaces of the enhancement elements and the package body are coplanar. The substrate includes first pads corresponding to the leads and second pads corresponding to the enhancement elements. The first solder joints are disposed between the first pads and the leads. The second solder joints are disposed between the second pads and the enhancement elements. The second solder joints contact side surfaces of the enhancement elements. The surface area of the second pads is greater than the surface area of the corresponding enhancement elements.

摘要翻译： 一种半导体器件封装，包括基板，第一和第二焊点，芯片焊盘，引线和围绕芯片焊盘的增强元件，与引线电连接的芯片以及封装芯片，引线部分和部分 的增强元件，但是留下每个增强元件的至少一个侧表面。 增强元件和封装主体的侧表面是共面的。 衬底包括对应于引线的第一焊盘和对应于增强元件的第二焊盘。 第一焊点设置在第一焊盘和引线之间。 第二焊点设置在第二焊盘和增强元件之间。 第二焊点接触增强元件的侧表面。 第二焊盘的表面积大于相应增强元件的表面积。

公开(公告)号：US20070290318A1

公开(公告)日：2007-12-20

申请号：US11845305

申请日：2007-08-27

申请人： Su TAO ,  Yu-Fang TSAI

发明人： Su TAO ,  Yu-Fang TSAI

IPC分类号： H01L23/02

CPC分类号： H01L25/03 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/4334 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The present invention relates to a multi-chip package structure, comprising a first substrate, a first chip, a sub-package and a first molding compound. The first chip is attached to the first substrate. The first molding compound encapsulates the first chip, the sub-package and the top surface of the first substrate. The bottom surface of the sub-package is attached to the first chip. The sub-package comprises a second substrate, a second chip and a second molding compound. -The second substrate has a top surface and a bottom surface, and is electrically connected to the first chip. The second chip is attached to the top surface of the second substrate to which the second chip is electrically connected. The second molding compound encapsulates the second chip and part of the top surface of the second substrate. Whereby, the relative large area caused by the parallel arrangement of a plurality of conventional package structures can be reduced, and there is no need to redesign signal-transmitting path.

摘要翻译： 本发明涉及一种多芯片封装结构，包括第一基板，第一芯片，子封装和第一模塑料。 第一芯片附接到第一基板。 第一模塑料封装第一芯片，子封装和第一衬底的顶表面。 子封装的底表面附接到第一芯片。 该子组件包括第二衬底，第二芯片和第二模塑料。 - 第二基板具有顶表面和底表面，并且电连接到第一芯片。 第二芯片附接到第二芯片电连接到的第二基板的顶表面。 第二模塑料包封第二芯片和第二基板顶表面的一部分。 由此，可以减少由多个常规封装结构的平行布置引起的相对大的面积，并且不需要重新设计信号传输路径。

公开(公告)号：US07129583B2

公开(公告)日：2006-10-31

申请号：US11026763

申请日：2004-12-31

申请人： Su Tao ,  Yu-Fang Tsai

发明人： Su Tao ,  Yu-Fang Tsai

IPC分类号： H01L23/02 ,  H01L25/065 ,  H01L25/10 ,  H01L25/03

CPC分类号： H01L25/03 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/4334 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The present invention relates to a multi-chip package structure, comprising a first substrate, a first chip, a sub-package and a first molding compound. The first chip is attached to the first substrate. The first molding compound encapsulates the first chip, the sub-package and the top surface of the first substrate. The bottom surface of the sub-package is attached to the first chip. The sub-package comprises a second substrate, a second chip and a second molding compound. The second substrate has a top surface and a bottom surface, and is electrically connected to the first chip. The second chip is attached to the top surface of the second substrate to which the second chip is electrically connected. The second molding compound encapsulates the second chip and part of the top surface of the second substrate. Whereby, the relative large area caused by the parallel arrangement of a plurality of conventional package structures can be reduced, and there is no need to redesign signal-transmitting path.

公开(公告)号：US20060131718A1

公开(公告)日：2006-06-22

申请号：US11353678

申请日：2006-02-14

申请人： Su Tao ,  Yu-Fang Tsai

发明人： Su Tao ,  Yu-Fang Tsai

IPC分类号： H01L23/02

CPC分类号： H01L25/03 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/4334 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The present invention relates to a multi-chip package structure, comprising a first substrate, a first chip, a sub-package and a first molding compound. The first chip is attached to the first substrate. The first molding compound encapsulates the first chip, the sub-package and the top surface of the first substrate. The bottom surface of the sub-package is attached to the first chip. The sub-package comprises a second substrate, a second chip and a second molding compound. The second substrate has a top surface and a bottom surface, and is electrically connected to the first chip. The second chip is attached to the top surface of the second substrate to which the second chip is electrically connected. The second molding compound encapsulates the second chip and part of the top surface of the second substrate. Whereby, the relative large area caused by the parallel arrangement of a plurality of conventional package structures can be reduced, and there is no need to redesign signal-transmitting path.