公开(公告)号：US09132523B2

公开(公告)日：2015-09-15

申请号：US13412260

申请日：2012-03-05

Applicant: Shen-Nan Lee ,  Ying-Mei Lin ,  Yu-Jen Cheng ,  Keung Hui ,  Huan-Just Lin

Inventor： Shen-Nan Lee ,  Ying-Mei Lin ,  Yu-Jen Cheng ,  Keung Hui ,  Huan-Just Lin

IPC: H01L21/302 ,  B24B49/12 ,  B24B37/013

CPC classification number: B24B37/013 ,  B24B49/12

Abstract: A method of performing chemical mechanical polish (CMP) processes on a wafer includes providing the wafer; determining a thickness profile of a feature on a surface of the wafer; and, after the step of determining the thickness profile, performing a high-rate CMP process on the feature using a polish recipe to substantially achieve a within-wafer thickness uniformity of the feature. The polish recipe is determined based on the thickness profile.

Abstract translation: 在晶片上进行化学机械抛光（CMP）工艺的方法包括提供晶片; 确定晶片表面上的特征的厚度分布; 并且在确定厚度分布的步骤之后，使用抛光配方对特征进行高速率CMP处理，以基本上实现特征的晶片内厚度均匀性。 根据厚度分布确定抛光配方。

公开(公告)号：US20130024019A1

公开(公告)日：2013-01-24

申请号：US13285679

申请日：2011-10-31

Applicant: Chien Rhone Wang ,  Tzu-Cheng Lin ,  Yu-Jen Cheng ,  Chih-Wei Lai ,  Hung-Pin Chang ,  Tsang-Jiuh Wu

Inventor： Chien Rhone Wang ,  Tzu-Cheng Lin ,  Yu-Jen Cheng ,  Chih-Wei Lai ,  Hung-Pin Chang ,  Tsang-Jiuh Wu

IPC: G05B13/04

CPC classification number: G05B19/41875 ,  G05B2219/32201 ,  G05B2219/32205 ,  G05B2219/45031 ,  Y02P90/20 ,  Y02P90/22

Abstract: Methods and apparatus for performing end point determination are disclosed. An embodiment includes an apparatus comprising a process tool and a programmable processor. The process tool has an output for signaling in-situ measurements of physical parameters during processing of a wafer in the process tool, and the process tool has an input for receiving a signal indicating a modification of a recipe for the processing. The programmable processor is for executing a virtual metrology model of the process tool to estimate an estimated characteristic of the wafer achieved during the processing. The estimated characteristic is based on the in-situ measurements and the virtual metrology model. The programmable processor has an output for transmitting the signal when the estimated characteristic exceeds a predetermined threshold based on a target characteristic.

Abstract translation: 公开了用于执行终点确定的方法和装置。 实施例包括一种包括处理工具和可编程处理器的装置。 处理工具具有用于在处理工具中的晶片处理期间信号化物理参数的原位测量的输出，并且处理工具具有用于接收指示用于处理的配方的修改的信号的输入。 可编程处理器用于执行处理工具的虚拟计量模型以估计在处理期间实现的晶片的估计特性。 估计的特征是基于原位测量和虚拟计量模型。 可编程处理器具有用于当估计特性基于目标特性超过预定阈值时发送信号的输出。

公开(公告)号：US20110112678A1

公开(公告)日：2011-05-12

申请号：US12616681

申请日：2009-11-11

Applicant: Chih-Wei Hsu ,  Yu-Jen Cheng ,  Wen-Pin Liu ,  Shun-Ping Wang ,  Shin-Rung Lu ,  Jo Fei Wang ,  Jong-I Mou ,  Andy Tsen ,  Chun-Hsien Lin

Inventor： Chih-Wei Hsu ,  Yu-Jen Cheng ,  Wen-Pin Liu ,  Shun-Ping Wang ,  Shin-Rung Lu ,  Jo Fei Wang ,  Jong-I Mou ,  Andy Tsen ,  Chun-Hsien Lin

IPC: G06F17/50

CPC classification number: H01L21/67253 ,  G05B19/41865 ,  H01L21/67276 ,  Y02P90/20

Abstract: The present disclosure provides a semiconductor manufacturing method. The method includes providing product data of a product, the product data including a sensitive product parameter; searching existing products according to the sensitive product parameter to identify a relevant product from the existing products; determining an initial value of a processing model parameter to the product using corresponding data of the relevant product; assigning the initial value of the processing model parameter to a processing model associated with a manufacturing process; thereafter, tuning a processing recipe using the processing model; and performing the manufacturing process to a semiconductor wafer using the processing recipe.

Abstract translation: 本发明提供一种半导体制造方法。 该方法包括提供产品的产品数据，产品数据包括敏感产品参数; 根据敏感产品参数搜索现有产品，从现有产品中识别相关产品; 使用相关产品的相应数据确定产品的处理模型参数的初始值; 将处理模型参数的初始值分配给与制造过程相关联的处理模型; 此后，使用该处理模型调整处理配方; 以及使用所述处理配方对所述半导体晶片进行制造处理。

公开(公告)号：US20100093259A1

公开(公告)日：2010-04-15

申请号：US12250239

申请日：2008-10-13

Applicant: Shen-Nan Lee ,  Ying-Mei Lin ,  Yu-Jen Cheng ,  Keung Hui ,  Huan-Just Lin

Inventor： Shen-Nan Lee ,  Ying-Mei Lin ,  Yu-Jen Cheng ,  Keung Hui ,  Huan-Just Lin

IPC: B24B49/04 ,  B24B49/12

CPC classification number: B24B37/013 ,  B24B49/12

Abstract: A method of performing chemical mechanical polish (CMP) processes on a wafer includes providing the wafer; determining a thickness profile of a feature on a surface of the wafer; and, after the step of determining the thickness profile, performing a high-rate CMP process on the feature using a polish recipe to substantially achieve a within-wafer thickness uniformity of the feature. The polish recipe is determined based on the thickness profile.

Abstract translation: 在晶片上进行化学机械抛光（CMP）工艺的方法包括提供晶片; 确定晶片表面上的特征的厚度分布; 并且在确定厚度分布的步骤之后，使用抛光配方对特征进行高速率CMP处理，以基本上实现特征的晶片内厚度均匀性。 根据厚度分布确定抛光配方。

公开(公告)号：US20090266601A1

公开(公告)日：2009-10-29

申请号：US12108678

申请日：2008-04-24

Applicant: Yu-Jen CHENG

Inventor： Yu-Jen CHENG

IPC: H05K9/00

CPC classification number: H05K9/003

Abstract: A protective cover for prevention of electromagnetism interference includes a shell and a metal cladding layer. The shell is comprised of a plastic material, and includes a base plate. An edge of the base plate bends upwardly with respect to the base plate and forms an enclosure plate. At least one separator is disposed on the base plate inside of the enclosure plate. The base plate, the enclosure plate and the at least one separator cooperatively define a plurality of isolation areas.

Abstract translation: 用于防止电磁干扰的保护罩包括壳体和金属覆层。 壳体由塑料材料构成，并包括基板。 基板的边缘相对于基板向上弯曲并形成外壳板。 至少一个分离器设置在外壳板内部的底板上。 基板，外壳板和至少一个分离器协作地限定多个隔离区域。

公开(公告)号：US20130023065A1

公开(公告)日：2013-01-24

申请号：US13189287

申请日：2011-07-22

Applicant: Chien Rhone Wang ,  Tzu-Cheng Lin ,  Yu-Jen Cheng ,  Chih-Wei Lai ,  Hung-Pin Chang ,  Tsang-Jiuh Wu

Inventor： Chien Rhone Wang ,  Tzu-Cheng Lin ,  Yu-Jen Cheng ,  Chih-Wei Lai ,  Hung-Pin Chang ,  Tsang-Jiuh Wu

IPC: H01L21/66

CPC classification number: H01J37/32963

Abstract: Methods and apparatus for performing end point determination. A method includes receiving a wafer into an etch tool chamber for performing an RIE etch; beginning the RIE etch to form vias in the wafer; receiving in-situ measurements of one or more physical parameters of the etch tool chamber that are correlated to the RIE etch process; providing a virtual metrology model for the RIE etch in the chamber; inputting the received in-situ measurements to the virtual metrology model for the RIE etch in the chamber; executing the virtual metrology model to estimate the current via depth; comparing the estimated current via depth to a target depth; and when the comparing indicates the current via depth is within a predetermined threshold of the target depth; outputting a stop signal. An apparatus for use with the method embodiment is disclosed.

Abstract translation: 执行终点确定的方法和装置。 一种方法包括将晶片接收到用于进行RIE蚀刻的蚀刻工具室中; 开始RIE蚀刻以在晶片中形成通孔; 接收与RIE蚀刻工艺相关的蚀刻工具室的一个或多个物理参数的原位测量; 为腔室中的RIE蚀刻提供虚拟计量模型; 将接收到的原位测量值输入到腔室中的RIE蚀刻的虚拟测量模型; 执行虚拟计量模型以通过深度估计电流; 将经过深度的估计电流与目标深度进行比较; 并且当比较指示当前经过深度在目标深度的预定阈值内时; 输出停止信号。 公开了一种用于该方法实施例的装置。

公开(公告)号：US08239056B2

公开(公告)日：2012-08-07

申请号：US12616681

申请日：2009-11-11

Applicant: Chih-Wei Hsu ,  Yu-Jen Cheng ,  Wen-Pin Liu ,  Shun-Ping Wang ,  Shin-Rung Lu ,  Jo Fei Wang ,  Jong-I Mou ,  Andy Tsen ,  Chun-Hsien Lin

Inventor： Chih-Wei Hsu ,  Yu-Jen Cheng ,  Wen-Pin Liu ,  Shun-Ping Wang ,  Shin-Rung Lu ,  Jo Fei Wang ,  Jong-I Mou ,  Andy Tsen ,  Chun-Hsien Lin

IPC: G06F19/00

CPC classification number: H01L21/67253 ,  G05B19/41865 ,  H01L21/67276 ,  Y02P90/20

Abstract: The present disclosure provides a semiconductor manufacturing method. The method includes providing product data of a product, the product data including a sensitive product parameter; searching existing products according to the sensitive product parameter to identify a relevant product from the existing products; determining an initial value of a processing model parameter to the product using corresponding data of the relevant product; assigning the initial value of the processing model parameter to a processing model associated with a manufacturing process; thereafter, tuning a processing recipe using the processing model; and performing the manufacturing process to a semiconductor wafer using the processing recipe.

Abstract translation: 本发明提供一种半导体制造方法。 该方法包括提供产品的产品数据，产品数据包括敏感产品参数; 根据敏感产品参数搜索现有产品，从现有产品中识别相关产品; 使用相关产品的相应数据确定产品的处理模型参数的初始值; 将处理模型参数的初始值分配给与制造过程相关联的处理模型; 此后，使用该处理模型调整处理配方; 以及使用所述处理配方对所述半导体晶片进行制造处理。

公开(公告)号：US20120106171A1

公开(公告)日：2012-05-03

申请号：US13176799

申请日：2011-07-06

Applicant: BILY WANG ,  SUNG-YI HSIAO ,  YU-JEN CHENG ,  JACK CHEN

Inventor： BILY WANG ,  SUNG-YI HSIAO ,  YU-JEN CHENG ,  JACK CHEN

IPC: F21V15/00

CPC classification number: H01L33/486 ,  H01L33/642 ,  H01L33/647 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/10253 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An LED package structure includes a conductive substrate unit, a first insulative unit, a second insulative unit, a light-emitting unit and a package unit. The conductive substrate unit includes at least two conductive bases and at least one gap is formed between the two conductive bases. The first insulative unit includes at least one first insulative layer filled in the gap to join the two conductive bases. The second insulative unit includes at least one second insulative layer disposed on the conductive substrate unit and a plurality of openings passing through the second insulative layer for exposing one part of the top surface of each conductive base. The light-emitting unit includes at least one light-emitting element passing one of the openings and electrically connected between the two conductive bases. The package unit includes a package resin body disposed on the second insulative unit to cover the light-emitting element.

Abstract translation: LED封装结构包括导电基板单元，第一绝缘单元，第二绝缘单元，发光单元和封装单元。 导电基板单元包括至少两个导电基底，并且在两个导电基底之间形成至少一个间隙。 第一绝缘单元包括填充在间隙中以连接两个导电基底的至少一个第一绝缘层。 第二绝缘单元包括设置在导电基板单元上的至少一个第二绝缘层和穿过第二绝缘层的多个开口，用于暴露每个导电基底的顶表面的一部分。 发光单元包括通过其中一个开口并电连接在两个导电基底之间的至少一个发光元件。 封装单元包括设置在第二绝缘单元上以覆盖发光元件的封装树脂体。

公开(公告)号：US08129279B2

公开(公告)日：2012-03-06

申请号：US12250239

申请日：2008-10-13

Applicant: Shen-Nan Lee ,  Ying-Mei Lin ,  Yu-Jen Cheng ,  Keung Hui ,  Huan-Just Lin

Inventor： Shen-Nan Lee ,  Ying-Mei Lin ,  Yu-Jen Cheng ,  Keung Hui ,  Huan-Just Lin

IPC: H01L21/302

CPC classification number: B24B37/013 ,  B24B49/12

Abstract: A method of performing chemical mechanical polish (CMP) processes on a wafer includes providing the wafer; determining a thickness profile of a feature on a surface of the wafer; and, after the step of determining the thickness profile, performing a high-rate CMP process on the feature using a polish recipe to substantially achieve a within-wafer thickness uniformity of the feature. The polish recipe is determined based on the thickness profile.

Abstract translation: 在晶片上进行化学机械抛光（CMP）工艺的方法包括提供晶片; 确定晶片表面上的特征的厚度分布; 并且在确定厚度分布的步骤之后，使用抛光配方对特征进行高速率CMP处理，以基本上实现特征的晶片内厚度均匀性。 根据厚度分布确定抛光配方。

公开(公告)号：US20120164918A1

公开(公告)日：2012-06-28

申请号：US13412260

申请日：2012-03-05

Applicant: Shen-Nan Lee ,  Ying-Mei Lin ,  Yu-Jen Cheng ,  Keung Hui ,  Huan-Just Lin

Inventor： Shen-Nan Lee ,  Ying-Mei Lin ,  Yu-Jen Cheng ,  Keung Hui ,  Huan-Just Lin

IPC: H01L21/302 ,  B24B49/12

CPC classification number: B24B37/013 ,  B24B49/12

Abstract: A method of performing chemical mechanical polish (CMP) processes on a wafer includes providing the wafer; determining a thickness profile of a feature on a surface of the wafer; and, after the step of determining the thickness profile, performing a high-rate CMP process on the feature using a polish recipe to substantially achieve a within-wafer thickness uniformity of the feature. The polish recipe is determined based on the thickness profile.

Abstract translation: 在晶片上进行化学机械抛光（CMP）工艺的方法包括提供晶片; 确定晶片表面上的特征的厚度分布; 并且在确定厚度分布的步骤之后，使用抛光配方对特征进行高速率CMP处理，以基本上实现特征的晶片内厚度均匀性。 根据厚度分布确定抛光配方。