公开(公告)号：US09477219B2

公开(公告)日：2016-10-25

申请号：US12731348

申请日：2010-03-25

Applicant: Chih-Wei Hsu ,  Jin-Ning Sung ,  Shin-Rung Lu ,  Jong-I Mou

Inventor： Chih-Wei Hsu ,  Jin-Ning Sung ,  Shin-Rung Lu ,  Jong-I Mou

IPC: G05B19/418

CPC classification number: G05B19/41875 ,  G05B2219/32017 ,  G05B2219/32189 ,  G05B2219/45031 ,  Y02P90/22

Abstract: A method of semiconductor fabrication is provided. The method includes providing a model for a device parameter of a wafer as a function of first and second process parameters. The first and second process parameters correspond to different wafer characteristics, respectively. The method includes deriving target values of the first and second process parameters based on a specified target value of the device parameter. The method includes performing a first fabrication process in response to the target value of the first process parameter. The method includes measuring an actual value of the first process parameter thereafter. The method includes updating the model using the actual value of the first process parameter. The method includes deriving a revised target value of the second process parameter using the updated model. The method includes performing a second fabrication process in response to the revised target value of the second process parameter.

Abstract translation: 提供了一种半导体制造方法。 该方法包括提供晶片的器件参数的模型作为第一和第二工艺参数的函数。 第一和第二工艺参数分别对应于不同的晶片特性。 该方法包括基于设备参数的指定目标值导出第一和第二处理参数的目标值。 该方法包括响应于第一过程参数的目标值执行第一制造过程。 该方法包括此后测量第一处理参数的实际值。 该方法包括使用第一过程参数的实际值更新模型。 该方法包括使用更新的模型导出第二过程参数的修正目标值。 该方法包括响应于修改的第二过程参数的目标值执行第二制造过程。

公开(公告)号：US08867018B2

公开(公告)日：2014-10-21

申请号：US12617403

申请日：2009-11-12

Applicant: Shin-Rung Lu ,  Tsai-Fu Ou ,  Wen-Yao Hsieh

Inventor： Shin-Rung Lu ,  Tsai-Fu Ou ,  Wen-Yao Hsieh

IPC: G03B27/68 ,  G03B27/32 ,  G03F7/20

CPC classification number: G03B27/32 ,  G03F7/70633 ,  G03F9/70

Abstract: A method for improving alignment in a photolithography machine is provided. The method comprises identifying first empirical alignment data that has been determined from use of a target photomask within at least one non-target tool, and identifying second empirical alignment data that has been determined from use of a non-target photomask within a target tool. The method continues by identifying third empirical alignment data that has been determined from use of a non-target photomask within at least one non-target tool, and calculating from the first, second, and third empirical alignment data a predicted alignment data for the target photomask with the target tool. The method then proceeds by aligning the target photomask within the target tool using the predicted alignment data, exposing a pattern from the target photomask onto the wafer in the target tool, and further processing the exposed wafer.

Abstract translation: 提供了一种用于改善光刻机中的对准的方法。 该方法包括识别在至少一个非目标工具内使用目标光掩模确定的第一经验对准数据，以及识别已经使用目标工具内的非目标光掩模确定的第二经验对准数据。 该方法通过识别在至少一个非目标工具中使用非目标光掩模确定的第三经验对准数据，并且从第一，第二和第三经验校准数据计算目标的预测对准数据 光掩模与目标工具。 该方法然后通过使用预测的对准数据将目标工具内的目标光掩模对准，将目标光掩模中的图案曝光到目标工具中的晶片上，并进一步处理暴露的晶片。

公开(公告)号：US08288063B2

公开(公告)日：2012-10-16

申请号：US12844507

申请日：2010-07-27

Applicant: Shin-Rung Lu ,  Chih Ming Hong ,  Yen-Di Tsen

Inventor： Shin-Rung Lu ,  Chih Ming Hong ,  Yen-Di Tsen

IPC: G03F9/00

CPC classification number: G03F7/70633 ,  G03F7/70525

Abstract: A method includes performing a lithography process on a wafer to form a patterned photo resist, and measuring the wafer to determine an overlay error of the patterned photo resist. A high/low specification is determined using the overlay error. An overlay process value setting is generated and compared with the high/low specification to determine whether the overlay process value setting is within a range defined by the high/low specification.

Abstract translation: 一种方法包括在晶片上进行光刻工艺以形成图案化光刻胶，并测量晶片以确定图案化光刻胶的重叠误差。 使用重叠错误确定高/低规格。 生成覆盖过程值设置并与高/低规格进行比较，以确定覆盖过程值设置是否在由高/低规格定义的范围内。

公开(公告)号：US07687211B2

公开(公告)日：2010-03-30

申请号：US11193126

申请日：2005-07-29

Applicant: Shui-Tien Lin ,  Shin-Rung Lu ,  Yi-Chuan Lo

Inventor： Shui-Tien Lin ,  Shin-Rung Lu ,  Yi-Chuan Lo

IPC: G03F9/00 ,  G03C5/00

CPC classification number: G03F7/70558 ,  G03F7/70533 ,  G03F7/70541

Abstract: A method for photolithography in semiconductor device manufacturing comprises defining test critical dimension target for a photolithography mask, measuring a mask critical dimension, comparing mask critical dimension to the test critical dimension target and determining a critical dimension deviation, determining a photolithography light base energy in response to the critical dimension deviation, and exposing the wafer according to the photolithography light base energy.

Abstract translation: 半导体器件制造中的光刻方法包括定义光刻掩模的测试临界尺寸目标，测量掩模临界尺寸，将掩模临界尺寸与测试临界尺寸目标进行比较并确定临界尺寸偏差，确定响应中的光刻光源能量 到临界尺寸偏差，并且根据光刻光基能量暴露晶片。

公开(公告)号：US20070066049A1

公开(公告)日：2007-03-22

申请号：US11230347

申请日：2005-09-20

Applicant: Shin-Rung Lu ,  Kun-Hong Lin

Inventor： Shin-Rung Lu ,  Kun-Hong Lin

IPC: H01L21/4763

CPC classification number: H01L21/76802 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/05559 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/05042 ,  H01L2924/14

Abstract: A method for patterning passivation layers including providing a semiconductor wafer comprising metal interconnects; forming a dielectric passivation layer on the metal interconnects; forming a photosensitive polymeric passivation layer on the dielectric passivation layer; patterning the photosensitive polymeric passivation layer in a first patterning process to form a first opening revealing a portion of the dielectric passivation layer; and, patterning the portion of the dielectric passivation layer in a second patterning process to form at least a second opening in the dielectric passivation layer.

Abstract translation: 一种用于构图钝化层的方法，包括提供包括金属互连的半导体晶片; 在金属互连上形成介电钝化层; 在所述电介质钝化层上形成光敏聚合物钝化层; 在第一图案化工艺中图案化光敏聚合物钝化层以形成透明电介质钝化层的一部分的第一开口; 以及在第二图案化工艺中图案化所述电介质钝化层的所述部分以在所述电介质钝化层中形成至少第二开口。

公开(公告)号：US20120028174A1

公开(公告)日：2012-02-02

申请号：US12844507

申请日：2010-07-27

Applicant: Shin-Rung Lu ,  Chih Ming Hong ,  Yen-Di Tsen

Inventor： Shin-Rung Lu ,  Chih Ming Hong ,  Yen-Di Tsen

IPC: G03F7/20

CPC classification number: G03F7/70633 ,  G03F7/70525

Abstract: A method includes performing a lithography process on a wafer to form a patterned photo resist, and measuring the wafer to determine an overlay error of the patterned photo resist. A high/low specification is determined using the overlay error. An overlay process value setting is generated and compared with the high/low specification to determine whether the overlay process value setting is within a range defined by the high/low specification.

Abstract translation: 一种方法包括在晶片上进行光刻工艺以形成图案化光刻胶，并测量晶片以确定图案化光刻胶的重叠误差。 使用重叠错误确定高/低规格。 生成覆盖过程值设置并与高/低规格进行比较，以确定覆盖过程值设置是否在由高/低规格定义的范围内。

公开(公告)号：US20060228865A1

公开(公告)日：2006-10-12

申请号：US11193126

申请日：2005-07-29

Applicant: Shui-Tien Lin ,  Shin-Rung Lu ,  Yi-Chuan Lo

Inventor： Shui-Tien Lin ,  Shin-Rung Lu ,  Yi-Chuan Lo

IPC: H01L21/76

CPC classification number: G03F7/70558 ,  G03F7/70533 ,  G03F7/70541

Abstract: A method for photolithography in semiconductor device manufacturing comprises defining test critical dimension target for a photolithography mask, measuring a mask critical dimension, comparing mask critical dimension to the test critical dimension target and determining a critical dimension deviation, determining a photolithography light base energy in response to the critical dimension deviation, and exposing the wafer according to the photolithography light base energy.

Abstract translation: 半导体器件制造中的光刻方法包括定义光刻掩模的测试临界尺寸目标，测量掩模临界尺寸，将掩模临界尺寸与测试临界尺寸目标进行比较并确定临界尺寸偏差，确定响应中的光刻光源能量 到临界尺寸偏差，并且根据光刻光基能量暴露晶片。

公开(公告)号：US07494928B2

公开(公告)日：2009-02-24

申请号：US11230347

申请日：2005-09-20

Applicant: Shin-Rung Lu ,  Kun-Hong Lin

Inventor： Shin-Rung Lu ,  Kun-Hong Lin

IPC: H01L21/302 ,  H01L21/461

CPC classification number: H01L21/76802 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/05559 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/05042 ,  H01L2924/14

Abstract: A method for patterning passivation layers including providing a semiconductor wafer comprising metal interconnects; forming a dielectric passivation layer on the metal interconnects; forming a photosensitive polymeric passivation layer on the dielectric passivation layer; patterning the photosensitive polymeric passivation layer in a first patterning process to form a first opening revealing a portion of the dielectric passivation layer; and, patterning the portion of the dielectric passivation layer in a second patterning process to form at least a second opening in the dielectric passivation layer.

Abstract translation: 一种用于构图钝化层的方法，包括提供包括金属互连的半导体晶片; 在金属互连上形成介电钝化层; 在所述电介质钝化层上形成光敏聚合物钝化层; 在第一图案化工艺中图案化光敏聚合物钝化层以形成透明电介质钝化层的一部分的第一开口; 以及在第二图案化工艺中图案化所述电介质钝化层的所述部分以在所述电介质钝化层中形成至少第二开口。

公开(公告)号：US20050054210A1

公开(公告)日：2005-03-10

申请号：US10656986

申请日：2003-09-04

Applicant: Shin-Rung Lu ,  Kun-Hong Lin

Inventor： Shin-Rung Lu ,  Kun-Hong Lin

IPC: G03C5/04 ,  G03F7/20 ,  H01L21/302 ,  H01L21/461

CPC classification number: G03F7/70283 ,  G03F1/00 ,  G03F7/70466

Abstract: A method for exposing a blanket photoresist layer employs exposing a minimum of two non-overlapping die sub-patterns within a single die region of the blanket photoresist layer, each exposed while employing a minimum of two separate masks. The use of the multiple masks and multiple sub-patterns provides upon development a patterned photoresist layer with enhanced dimensional precision and uniformity.

Abstract translation: 用于曝光橡皮布光致抗蚀剂层的方法采用在橡皮布光致抗蚀剂层的单个管芯区域内露出最少两个非重叠的裸片子图案，每一裸片区域在使用至少两个分开的掩模的同时露出。 使用多个掩模和多个子图案提供了具有增强的尺寸精度和均匀性的图案化的光致抗蚀剂层。

公开(公告)号：US08239056B2

公开(公告)日：2012-08-07

申请号：US12616681

申请日：2009-11-11

Applicant: Chih-Wei Hsu ,  Yu-Jen Cheng ,  Wen-Pin Liu ,  Shun-Ping Wang ,  Shin-Rung Lu ,  Jo Fei Wang ,  Jong-I Mou ,  Andy Tsen ,  Chun-Hsien Lin

Inventor： Chih-Wei Hsu ,  Yu-Jen Cheng ,  Wen-Pin Liu ,  Shun-Ping Wang ,  Shin-Rung Lu ,  Jo Fei Wang ,  Jong-I Mou ,  Andy Tsen ,  Chun-Hsien Lin

IPC: G06F19/00

CPC classification number: H01L21/67253 ,  G05B19/41865 ,  H01L21/67276 ,  Y02P90/20

Abstract: The present disclosure provides a semiconductor manufacturing method. The method includes providing product data of a product, the product data including a sensitive product parameter; searching existing products according to the sensitive product parameter to identify a relevant product from the existing products; determining an initial value of a processing model parameter to the product using corresponding data of the relevant product; assigning the initial value of the processing model parameter to a processing model associated with a manufacturing process; thereafter, tuning a processing recipe using the processing model; and performing the manufacturing process to a semiconductor wafer using the processing recipe.

Abstract translation: 本发明提供一种半导体制造方法。 该方法包括提供产品的产品数据，产品数据包括敏感产品参数; 根据敏感产品参数搜索现有产品，从现有产品中识别相关产品; 使用相关产品的相应数据确定产品的处理模型参数的初始值; 将处理模型参数的初始值分配给与制造过程相关联的处理模型; 此后，使用该处理模型调整处理配方; 以及使用所述处理配方对所述半导体晶片进行制造处理。