公开(公告)号：US20120267779A1

公开(公告)日：2012-10-25

申请号：US13430439

申请日：2012-03-26

申请人： Tzu-Hung LIN ,  Wen-Sung HSU ,  Tai-Yu CHEN

发明人： Tzu-Hung LIN ,  Wen-Sung HSU ,  Tai-Yu CHEN

IPC分类号： H01L23/498

CPC分类号： H01L24/14 ,  H01L23/3192 ,  H01L23/49838 ,  H01L24/04 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/02125 ,  H01L2224/02165 ,  H01L2224/02166 ,  H01L2224/02181 ,  H01L2224/0219 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/11462 ,  H01L2224/13006 ,  H01L2224/13016 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/14515 ,  H01L2224/16238 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/07025 ,  H01L2924/18161 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2224/05552

摘要： The invention provides a semiconductor package. The semiconductor package includes a semiconductor die having a central area and a peripheral area surrounding the central area. A first conductive bump is disposed on the semiconductor die in the central area. A second conductive bump is disposed on the semiconductor die in the peripheral area. An area ratio of the first conductive bump to the second conductive bump from a top view is larger than 1, and less than or equal to 3.

摘要翻译： 本发明提供一种半导体封装。 半导体封装包括具有中心区域和围绕中心区域的周边区域的半导体管芯。 第一导电凸块设置在中心区域的半导体管芯上。 第二导电凸块设置在周边区域的半导体管芯上。 从顶视图看，第一导电凸块与第二导电凸块的面积比大于1，小于或等于3。

公开(公告)号：US20110115083A1

公开(公告)日：2011-05-19

申请号：US12621839

申请日：2009-11-19

申请人： Ruey Kae Zang ,  Wen-Sung Hsu

发明人： Ruey Kae Zang ,  Wen-Sung Hsu

IPC分类号： H01L23/28 ,  H01L21/56

CPC分类号： H01L21/563 ,  H01L2224/16225 ,  H01L2224/26175 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83385 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00

摘要： A packaging system for preventing underfill overflow includes a package substrate having a solder mask a die attach site, a solder mask dam on the solder mask proximal to the die attach site, and a trench in the solder mask proximal to the die attach site. The trench and the solder mask dam are adapted to constrain flow of an underfill material.

摘要翻译： 用于防止底部填充溢出的包装系统包括具有焊接掩模，管芯附着部位的封装基板，在焊盘附近位置附近的焊料掩模上的焊接掩模，以及在焊料掩模附近的管芯附着位置处的沟槽。 沟槽和焊盘掩模适于限制底部填充材料的流动。

公开(公告)号：US07465885B2

公开(公告)日：2008-12-16

申请号：US10817580

申请日：2004-04-02

申请人： Ming-Ren Chi ,  Wen-Sung Hsu

发明人： Ming-Ren Chi ,  Wen-Sung Hsu

IPC分类号： H05K1/16

CPC分类号： H05K3/3452 ,  H05K3/284 ,  H05K2201/0989 ,  H05K2201/10636 ,  Y02P70/611

摘要： A circuit carrier is provided. The circuit carrier includes a substrate, a patterned circuit layer, and a solder mask layer. The patterned circuit layer is deposed on a surface of the substrate and has two passive component electrode pads. The solder mask layer covers the surface of the substrate, and includes a first solder mask opening, a second solder mask opening, and a third solder mask opening. The first solder mask opening and the second solder mask opening expose the passive component electrode pads respectively. The third solder mask opening along its length direction is divided into a central area and two extension areas. The central area is between the first and the second solder mask openings. The extension areas are extending from the central area along the length direction to two sides, respectively. The width of the central area is smaller than the width of one the extension areas.

摘要翻译： 提供电路载体。 电路载体包括衬底，图案化电路层和焊料掩模层。 图案化电路层被放置在衬底的表面上并且具有两个无源部件电极焊盘。 焊料掩模层覆盖基板的表面，并且包括第一焊料掩模开口，第二焊接掩模开口和第三焊接掩模开口。 第一焊料掩模开口和第二焊接掩模开口分别暴露无源元件电极焊盘。 沿其长度方向的第三焊料掩模开口被分成中心区域和两个延伸区域。 中心区域位于第一和第二焊料掩模开口之间。 延伸区域分别从中心区域沿着长度方向延伸到两侧。 中心区域的宽度小于扩展区域的宽度。

公开(公告)号：US08952552B2

公开(公告)日：2015-02-10

申请号：US12621839

申请日：2009-11-19

申请人： Ruey Kae Zang ,  Wen-Sung Hsu

发明人： Ruey Kae Zang ,  Wen-Sung Hsu

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/28 ,  H01L21/56

CPC分类号： H01L21/563 ,  H01L2224/16225 ,  H01L2224/26175 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83385 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00

摘要： A packaging system for preventing underfill overflow includes a package substrate having a solder mask a die attach site, a solder mask dam on the solder mask proximal to the die attach site, and a trench in the solder mask proximal to the die attach site. The trench and the solder mask dam are adapted to constrain flow of an underfill material.

摘要翻译： 用于防止底部填充溢出的包装系统包括具有焊接掩模，管芯附着部位的封装基板，在焊盘附近位置附近的焊料掩模上的焊接掩模，以及在焊料掩模附近的管芯附着位置处的沟槽。 沟槽和焊盘掩模适于限制底部填充材料的流动。

公开(公告)号：US20050145412A1

公开(公告)日：2005-07-07

申请号：US10817580

申请日：2004-04-02

申请人： Ming-Ren Chi ,  Wen-Sung Hsu

发明人： Ming-Ren Chi ,  Wen-Sung Hsu

IPC分类号： H05K3/28 ,  H05K3/34 ,  H05K1/18

CPC分类号： H05K3/3452 ,  H05K3/284 ,  H05K2201/0989 ,  H05K2201/10636 ,  Y02P70/611

摘要： A circuit carrier is provided. The circuit carrier comprises a substrate, a patterned circuit layer, and a solder mask layer. The patterned circuit layer is deposed on a surface of the substrate and has two passive component electrode pads. The solder mask layer covers the surface of the substrate, and includes a first solder mask opening, a second solder mask opening, and a third solder mask opening. The first solder mask opening and the second solder mask opening expose the passive component electrode pads respectively. The third solder mask opening along its length direction is divided into a central area and two extension areas. The central area is between the first and the second solder mask openings. The extension areas are extending from the central area along the length direction to two sides, respectively. The width of the central area is smaller than the width of one the extension areas.

摘要翻译： 提供电路载体。 电路载体包括衬底，图案化电路层和焊料掩模层。 图案化电路层被放置在衬底的表面上并且具有两个无源部件电极焊盘。 焊料掩模层覆盖基板的表面，并且包括第一焊料掩模开口，第二焊接掩模开口和第三焊接掩模开口。 第一焊料掩模开口和第二焊接掩模开口分别暴露无源元件电极焊盘。 沿其长度方向的第三焊料掩模开口被分成中心区域和两个延伸区域。 中心区域位于第一和第二焊料掩模开口之间。 延伸区域分别从中心区域沿着长度方向延伸到两侧。 中心区域的宽度小于扩展区域的宽度。