公开(公告)号：US08669184B2

公开(公告)日：2014-03-11

申请号：US13012506

申请日：2011-01-24

Applicant: Tuung Luoh ,  Ling-Wu Yang ,  Ta-Hone Yang ,  Kuang-Chao Chen

Inventor： Tuung Luoh ,  Ling-Wu Yang ,  Ta-Hone Yang ,  Kuang-Chao Chen

IPC: H01L21/302

CPC classification number: H01L21/02068 ,  H01L21/0217 ,  H01L21/32055 ,  H01L21/32139 ,  H01L21/76834

Abstract: Described is a method for improving the flatness of a layer deposited on a doped polycrystalline layer, which includes reducing the grain size of the polycrystalline layer to decrease the out-diffusion amount of the dopant from the polycrystalline layer, and/or reducing the amount of the out-diffusing dopant on the surface of the polycrystalline layer.

Abstract translation: 描述了一种用于提高沉积在掺杂多晶层上的层的平坦度的方法，其包括减小多晶层的晶粒尺寸以减少掺杂剂从多晶层的扩散量，和/或减少 多晶层表面上的扩散扩散掺杂剂。

公开(公告)号：US08653592B2

公开(公告)日：2014-02-18

申请号：US13291374

申请日：2011-11-08

Applicant: Ming-Da Cheng ,  Chin-Tsan Yeh ,  Tuung Luoh ,  Chin-Ta Su ,  Ta-Hung Yang ,  Kuang-Chao Chen

Inventor： Ming-Da Cheng ,  Chin-Tsan Yeh ,  Tuung Luoh ,  Chin-Ta Su ,  Ta-Hung Yang ,  Kuang-Chao Chen

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/76 ,  H01L29/792

CPC classification number: H01L21/76229 ,  H01L21/76205

Abstract: A method of forming an isolation structure, comprising: (a) providing a base having a recess; (b) forming a stop layer on the base and in the recess; (c) forming a dielectric material on the stop layer so as to allow the rest of the recess to be filled with the dielectric material; (d) removing the dielectric material over the base by performing a chemical mechanical polishing (CMP) process until a part of the stop layer is exposed so as to form a dielectric layer in the recess; and (e) removing a part of the stop layer, wherein the another part of the stop layer and the dielectric layer filled in the recess constitute the isolation structure.

Abstract translation: 一种形成隔离结构的方法，包括：（a）提供具有凹部的基部; （b）在基座和凹槽中形成停止层; （c）在所述阻挡层上形成电介质材料，以允许所述凹部的其余部分填充所述电介质材料; （d）通过进行化学机械抛光（CMP）工艺在基底上去除电介质材料，直到一部分停止层被暴露以在凹槽中形成电介质层; 和（e）去除所述阻挡层的一部分，其中所述阻挡层的另一部分和填充在所述凹部中的所述电介质层构成所述隔离结构。

公开(公告)号：US08520194B2

公开(公告)日：2013-08-27

申请号：US12248547

申请日：2008-10-09

Applicant: Tuung Luoh ,  Sheng-Hui Hsieh ,  Shing-Ann Luo ,  Chin-Ta Su ,  Ta-Hung Yang ,  Kuang-Chao Chen

Inventor： Tuung Luoh ,  Sheng-Hui Hsieh ,  Shing-Ann Luo ,  Chin-Ta Su ,  Ta-Hung Yang ,  Kuang-Chao Chen

IPC: G01N21/00

CPC classification number: H01J37/32972 ,  G01N21/68 ,  H01J37/32935

Abstract: An advance process control (APC) system for a plasma process machine is provided, which includes at least an optical emission spectroscopy (OES) system and an APC analysis apparatus. The OES system is used for monitoring a testing object in the plasma process machine. The APC analysis apparatus is used for analyzing the data received from the OES system.

Abstract translation: 提供了一种用于等离子体处理机的先进过程控制（APC）系统，其包括至少一个光发射光谱（OES）系统和APC分析装置。 OES系统用于监测等离子体处理机中的测试对象。 APC分析装置用于分析从OES系统接收到的数据。

公开(公告)号：US20120074401A1

公开(公告)日：2012-03-29

申请号：US12892479

申请日：2010-09-28

Applicant: Che-Lun Hung ,  Hsiang-Chou Liao ,  Tuung Luoh ,  Ling-Wu Yang

Inventor： Che-Lun Hung ,  Hsiang-Chou Liao ,  Tuung Luoh ,  Ling-Wu Yang

IPC: H01L23/48 ,  H01L21/66

CPC classification number: G11C29/56 ,  G11C29/006

Abstract: A method of detecting manufacturing defects at a memory array may include disposing an active area of a first width in communication with a first conductive member of the memory array to define a grounded conductive member, disposing an isolation structure of a second width in communication with a second conductive member of the memory array to define a floating conductive member, and providing an alternating arrangement of floating and grounded conductive members including arranging a plurality of the grounded and floating conductive members adjacent to each other to define a sequence of alternating floating and grounded conductive members. A corresponding test device is also provided.

Abstract translation: 检测存储器阵列中的制造缺陷的方法可以包括将与存储器阵列的第一导电构件连通的第一宽度的有源区域设置为限定接地导电构件，将与第二宽度的隔离结构 存储器阵列的第二导电构件以限定浮动导电构件，以及提供浮动和接地导电构件的交替布置，包括布置彼此相邻的多个接地和浮动导电构件，以限定一系列交替的浮动和接地导电 会员 还提供了相应的测试装置。

公开(公告)号：US20120049269A1

公开(公告)日：2012-03-01

申请号：US13291374

申请日：2011-11-08

Applicant: Ming-Da Cheng ,  Chin-Tsan Yeh ,  Tuung Luoh ,  Chin-Ta Su ,  Ta-Hung Yang ,  Kuang-Chao Chen

Inventor： Ming-Da Cheng ,  Chin-Tsan Yeh ,  Tuung Luoh ,  Chin-Ta Su ,  Ta-Hung Yang ,  Kuang-Chao Chen

IPC: H01L29/792 ,  H01L29/06

CPC classification number: H01L21/76229 ,  H01L21/76205

Abstract: A method of forming an isolation structure, comprising: (a) providing a base having a recess; (b) forming a stop layer on the base and in the recess; (c) forming a dielectric material on the stop layer so as to allow the rest of the recess to be filled with the dielectric material; (d) removing the dielectric material over the base by performing a chemical mechanical polishing (CMP) process until a part of the stop layer is exposed so as to form a dielectric layer in the recess; and (e) removing a part of the stop layer, wherein the another part of the stop layer and the dielectric layer filled in the recess constitute the isolation structure.

Abstract translation: 一种形成隔离结构的方法，包括：（a）提供具有凹部的基部; （b）在基座和凹槽中形成停止层; （c）在所述阻挡层上形成电介质材料，以允许所述凹部的其余部分填充所述电介质材料; （d）通过进行化学机械抛光（CMP）工艺在基底上去除电介质材料，直到一部分停止层被暴露以在凹槽中形成电介质层; 和（e）去除所述阻挡层的一部分，其中所述阻挡层的另一部分和填充在所述凹部中的所述电介质层构成所述隔离结构。

公开(公告)号：US08034691B2

公开(公告)日：2011-10-11

申请号：US12193442

申请日：2008-08-18

Applicant: Tuung Luoh ,  Chin-Ta Su ,  Ta-Hung Yang ,  Kuang-Chao Chen ,  Shing-Ann Luo

Inventor： Tuung Luoh ,  Chin-Ta Su ,  Ta-Hung Yang ,  Kuang-Chao Chen ,  Shing-Ann Luo

IPC: H01L21/336

CPC classification number: H01L21/31608 ,  C23C16/0209 ,  C23C16/045 ,  C23C16/401 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/76224

Abstract: An HDP-CVD process is described, including a deposition step conducted in an HDP-CVD chamber and a pre-heating step that is performed outside of the HDP-CVD chamber before the deposition step and pre-heats a wafer to a temperature higher than room temperature and required in the HDP-CVD process deposition step.

Abstract translation: 描述了HDP-CVD工艺，包括在HDP-CVD室内进行的沉积步骤和在沉积步骤之前在HDP-CVD室外进行的预热步骤，并将晶片预热至高于 室温，并且在HDP-CVD工艺沉积步骤中是必需的。

公开(公告)号：US07517780B2

公开(公告)日：2009-04-14

申请号：US11044212

申请日：2005-01-28

Applicant: Ling-Wuu Yang ,  Kuang-Chao Chen ,  Tuung Luoh

Inventor： Ling-Wuu Yang ,  Kuang-Chao Chen ,  Tuung Luoh

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L21/44

CPC classification number: H01L21/28052 ,  H01L21/32155 ,  H01L29/66575

Abstract: A method of manufacturing a semiconductor device includes providing a first layer over a wafer substrate, providing a polysilicon layer over the first layer, implanting nitrogen ions into the polysilicon layer, forming a polycide layer over the polysilicon layer, and forming source and drain regions.

Abstract translation: 一种制造半导体器件的方法包括在晶片衬底上提供第一层，在第一层上提供多晶硅层，将氮离子注入到多晶硅层中，在多晶硅层上形成多晶硅化物层，以及形成源区和漏极区。

公开(公告)号：US20080119042A1

公开(公告)日：2008-05-22

申请号：US11847135

申请日：2007-08-29

Applicant: Tuung Luoh ,  Chi-Tung Huang ,  Kuang-Chao Chen ,  Candy Jiang

Inventor： Tuung Luoh ,  Chi-Tung Huang ,  Kuang-Chao Chen ,  Candy Jiang

IPC: H01L21/4763

CPC classification number: H01L21/76843 ,  H01L21/76864 ,  H01L21/76877

Abstract: A BEOL manufacturing process for forming a via process between two metal lines on a semiconductor wafer comprises depositing a portion of a first metal adhesion layer within a patterned via hole, followed by a cooling step. The cooling step is then followed by formation of the remainder of the first metal adhesion layer and formation of a second metal adhesion layer within the patterned via hole. This process of forming the remaining portion of the first metal adhesion layer can be referred to as a wafer load, unload, load (LUL) process. By using a LUL process, thermal history is minimized, which reduces Al extrusion at the via interfaces.

Abstract translation: 用于在半导体晶片上的两个金属线之间形成通孔工艺的BEOL制造工艺包括在图案化的通孔内沉积第一金属粘附层的一部分，接着进行冷却步骤。 然后冷却步骤之后形成第一金属粘合层的其余部分，并在图案化的通孔内形成第二金属粘合层。 形成第一金属粘合层的剩余部分的这个过程可以被称为晶片负载，卸载，负载（LUL）过程。 通过使用LUL工艺，可以最大限度地减少热历史，从而减少通孔界面处的Al挤压。

公开(公告)号：US20070161204A1

公开(公告)日：2007-07-12

申请号：US11329553

申请日：2006-01-11

Applicant: Hsing-Hua Chiu ,  Tuung Luoh ,  Chi-Tung Huang ,  Kuang-Chao Chen

Inventor： Hsing-Hua Chiu ,  Tuung Luoh ,  Chi-Tung Huang ,  Kuang-Chao Chen

IPC: H01L21/76

CPC classification number: H01L23/53223 ,  H01L21/0276 ,  H01L21/2855 ,  H01L21/32051 ,  H01L21/32139 ,  H01L2924/0002 ,  Y10S438/952 ,  H01L2924/00

Abstract: A process for forming an ARC layer in the fabrication of a semiconductor device comprises forming a modified ARC layer that increases the resistance to crown defects and bridging and also provides better adhesion for the ARC layer with the underlying metal layer. The modified ARC layer can comprise two titanium nitride ARC layers, a titanium nitride/titanium/titanium nitride sandwich structure, a modified titanium nitride layer, or an extended thickness titanium nitride layer.

Abstract translation: 在制造半导体器件中形成ARC层的方法包括形成改进的ARC层，其增加了对冠部缺陷和桥接的抵抗性，并且还为具有下面的金属层的ARC层提供了更好的附着力。 经修改的ARC层可以包括两个氮化钛ARC层，氮化钛/钛/氮化钛夹层结构，改性氮化钛层或延伸厚度的氮化钛层。

公开(公告)号：US08184288B2

公开(公告)日：2012-05-22

申请号：US12540001

申请日：2009-08-12

Applicant: Tuung Luoh ,  Sheng-Hui Hsieh ,  Shing-Ann Luo ,  Chin-Ta Su ,  Ta-Hung Yang ,  Kuang-Chao Chen

Inventor： Tuung Luoh ,  Sheng-Hui Hsieh ,  Shing-Ann Luo ,  Chin-Ta Su ,  Ta-Hung Yang ,  Kuang-Chao Chen

IPC: G01J3/30

CPC classification number: H01J37/32972 ,  G01N21/68 ,  H01J37/32935

Abstract: An advance process control (APC) system for a plasma process machine is provided, which includes at least an optical emission spectroscopy (OES) system and an APC analysis apparatus. The OES system is used for monitoring a testing object in the plasma process machine. The APC analysis apparatus is used for analyzing the data received from the OES system.

Abstract translation: 提供了一种用于等离子体处理机的先进过程控制（APC）系统，其包括至少一个光发射光谱（OES）系统和APC分析装置。 OES系统用于监测等离子体处理机中的测试对象。 APC分析装置用于分析从OES系统接收到的数据。