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    Radiation hardened semiconductor memory
    1.
    发明授权
    Radiation hardened semiconductor memory 失效
    辐射硬化半导体存储器

    公开(公告)号：US6091630A

    公开(公告)日：2000-07-18

    申请号：US393125

    申请日：1999-09-10

    申请人： Tsiu C. Chan ,  Mehdi Zamanian

    发明人： Tsiu C. Chan ,  Mehdi Zamanian

    IPC分类号： H01L21/8244 ,  H01L27/11 ,  G11C11/00

    CPC分类号： H01L27/1104

    摘要： A radiation hardened memory device having static random access memory cells includes active gate isolation structures placed in series with oxide isolation regions between the active regions of a memory cell array. The active gate isolation structure includes a gate oxide and polycrystalline silicon gate layer electrically coupled to a supply terminal resulting in an active gate isolation structure that prevents a conductive channel extending from adjacent active regions from forming. The gate oxide of the active gate isolation structures is relatively thin compared to the conventional oxide isolation regions and thus, will be less susceptible to any adverse influence from trapped charges caused by radiation exposure.

    摘要翻译： 具有静态随机存取存储器单元的辐射硬化存储器件包括与存储器单元阵列的有源区之间的氧化物隔离区域串联设置的有源栅极隔离结构。 有源栅极隔离结构包括电耦合到电源端的栅极氧化物和多晶硅栅极层，导致有源栅极隔离结构，其防止从相邻的有源区域延伸的导电沟道形成。 与常规的氧化物隔离区域相比，有源栅极隔离结构的栅极氧化物相对较薄，因此不太容易受到由辐射暴露引起的俘获电荷的任何不利影响。

    Local interconnect structure
    3.
    发明授权
    Local interconnect structure 失效
    本地互连结构

    公开(公告)号：US5489797A

    公开(公告)日：1996-02-06

    申请号：US420353

    申请日：1995-04-11

    申请人： Tsiu C. Chan ,  Frank R. Bryant ,  John L. Walters

    发明人： Tsiu C. Chan ,  Frank R. Bryant ,  John L. Walters

    IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L27/11 ,  H01L29/76 ,  H01L29/94

    CPC分类号： H01L27/1104 ,  H01L21/76895 ,  H01L23/53271 ,  H01L2924/0002 ,  Y10S257/903

    摘要： An interconnect structure, and method for forming same, is suitable for use in integrated circuits such as SRAM devices. The structure uses masking of a polycrystalline silicon interconnect level to move a P-N junction to a region within a polycrystalline silicon interconnect line, rather than at the substrate. This P-N junction can then be shorted out using a refractory metal silicide formed on the polycrystalline silicon interconnect structure.

    摘要翻译： 互连结构及其形成方法适用于诸如SRAM器件的集成电路。 该结构使用多晶硅互连电平的掩模将P-N结移动到多晶硅互连线内的区域，而不是在衬底处。 然后可以使用形成在多晶硅互连结构上的难熔金属硅化物来短路该P-N结。

    Capacitor for DRAM cell
    4.
    发明授权
    Capacitor for DRAM cell 失效
    DRAM单元电容器

    公开(公告)号：US5196909A

    公开(公告)日：1993-03-23

    申请号：US697227

    申请日：1991-05-07

    申请人： Tsiu C. Chan ,  Frank R. Bryant

    发明人： Tsiu C. Chan ,  Frank R. Bryant

    IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10844 ,  H01L27/10817 ,  H01L28/40

    摘要： A capacitor suitable for use with a DRAM memory cell is composed of multiple layers of polycrystalline silicon. The storage node is formed from a polycrystalline silicon layer sandwiched between two polysilicon ground plate layers. Such a structure nearly doubles the capacitance for a given chip surface area used. First the bottom polycrystalline silicon plate layer is fabricated, followed by an isolation step and fabrication of the storage node polycrystalline silicon layer. Following another isolation step, the polycrystalline silicon top plate layer is then formed and connected to the bottom plate layer.

    摘要翻译： 适用于DRAM存储单元的电容器由多层多晶硅组成。 存储节点由夹在两个多晶硅接地板层之间的多晶硅层形成。 这种结构对于所使用的给定芯片表面积几乎使电容增加一倍。 首先制造底部多晶硅板层，然后进行隔离步骤和存储节点多晶硅层的制造。 在另一隔离步骤之后，然后形成多晶硅顶板层并将其连接到底板层。

    Contact in an integrated circuit
    6.
    发明授权
    Contact in an integrated circuit 失效
    在集成电路中接触

    公开(公告)号：US06580133B2

    公开(公告)日：2003-06-17

    申请号：US09923746

    申请日：2001-08-07

    申请人： Tsiu C. Chan ,  Kuei-Wu Huang

    发明人： Tsiu C. Chan ,  Kuei-Wu Huang

    IPC分类号： H01L2976

    CPC分类号： H01L21/76802

    摘要： A method is provided for forming an improved contact opening of a semiconductor integrated circuit, and an integrated circuit formed according to the same. Planarization of the semiconductor structure is maximized and misalignment of contact openings is tolerated by first forming a conductive structure over a portion of a first body. A thin dielectric layer is formed at least partially over the conductive structure. A thick film, having a high etch selectivity to the thin dielectric layer, is formed over the dielectric layer. The thick film is patterned and etched to form a stack substantially over the conductive structure. An insulation layer is formed over the thin dielectric layer and the stack wherein the stack has a relatively high etch selectivity to the insulation layer. The insulation layer is etched back to expose an upper surface of the stack. The stack is then etched to form an opening in the insulation layer exposing the thin dielectric layer which acts as an etch stop during the stack etch process. The thin dielectric layer is then etched in the opening to expose the first conductive layer. A conductor is then formed in the opening contacting the underlying conductive structure. The thin dielectric under the insulation layer and on the sides of the opening near the conductive structure will increase the distance and help to electrically isolate the conductor at the edge of the contact opening from nearby active areas and devices.

    摘要翻译： 提供一种用于形成半导体集成电路的改进的接触开口的方法和根据该集成电路形成的集成电路。 半导体结构的平面化最大化，并且通过首先在第一体的一部分上形成导电结构来容许接触开口的不对准。 至少部分地在导电结构上形成薄介电层。 在介电层上形成对薄介电层具有高蚀刻选择性的厚膜。 对厚膜进行图案化和蚀刻以形成基本上在导电结构上的叠层。 绝缘层形成在薄介电层和堆叠上，其中堆叠对绝缘层具有相对高的蚀刻选择性。 绝缘层被回蚀以暴露堆叠的上表面。 然后对叠层进行蚀刻，以在绝缘层中形成露出薄层电介质层的开口，该薄介电层在叠层蚀刻工艺期间用作蚀刻停止层。 然后在开口中蚀刻薄介电层以暴露第一导电层。 然后在与下面的导电结构接触的开口中形成导体。 绝缘层下方的绝缘层和靠近导电结构的开口侧面的薄电介质将增加距离，并有助于将导体在接触开口的边缘与附近的有源区域和器件电隔离。

    Method of forming a contact in an integrated circuit
    7.
    发明授权
    Method of forming a contact in an integrated circuit 失效
    在集成电路中形成触点的方法

    公开(公告)号：US06297110B1

    公开(公告)日：2001-10-02

    申请号：US08282730

    申请日：1994-07-29

    申请人： Tsiu C. Chan ,  Kuei-Wu Huang

    发明人： Tsiu C. Chan ,  Kuei-Wu Huang

    IPC分类号： H01L21336

    CPC分类号： H01L21/76802

    摘要： A method is provided for forming an improved contact opening of a semiconductor integrated circuit, and an integrated circuit formed according to the same. Planarization of the semiconductor structure is maximized and misalignment of contact openings is tolerated by first forming a conductive structure over a portion of a first body. A thin dielectric layer is formed at least partially over the conductive structure. A thick film, having a high etch selectivity to the thin dielectric layer, is formed over the dielectric layer. The thick film is patterned and etched to form a stack substantially over the conductive structure. An insulation layer is formed over the thin dielectric layer and the stack wherein the stack has a relatively high etch selectivity to the insulation layer. The insulation layer is etched back to expose an upper surface of the stack. The stack is then etched to form an opening in the insulation layer exposing the thin dielectric layer which acts as an etch stop during the stack etch process. The thin dielectric layer is then etched in the opening to expose the first conductive layer. A conductor is then formed in the opening contacting the underlying conductive structure. The thin dielectric under the insulation layer and on the sides of the opening near the conductive structure will increase the distance and help to electrically isolate the conductor at the edge of the contact opening from nearby active areas and devices.

    摘要翻译： 提供一种用于形成半导体集成电路的改进的接触开口的方法和根据该集成电路形成的集成电路。 半导体结构的平面化最大化，并且通过首先在第一体的一部分上形成导电结构来容许接触开口的不对准。 至少部分地在导电结构上形成薄介电层。 在介电层上形成对薄介电层具有高蚀刻选择性的厚膜。 对厚膜进行图案化和蚀刻以形成基本上在导电结构上的叠层。 绝缘层形成在薄介电层和堆叠上，其中堆叠对绝缘层具有相对高的蚀刻选择性。 绝缘层被回蚀以暴露堆叠的上表面。 然后对叠层进行蚀刻，以在绝缘层中形成露出薄层电介质层的开口，该薄介电层在叠层蚀刻工艺期间用作蚀刻停止层。 然后在开口中蚀刻薄介电层以暴露第一导电层。 然后在与下面的导电结构接触的开口中形成导体。 绝缘层下方的绝缘层和靠近导电结构的开口侧面的薄电介质将增加距离，并有助于将导体在接触开口的边缘与附近的有源区域和器件电隔离。

    Method for forming planarized multilevel metallization in an integrated circuit
    8.
    发明授权
    Method for forming planarized multilevel metallization in an integrated circuit 失效
    在集成电路中形成平面化多层金属化的方法

    公开(公告)号：US06180509B2

    公开(公告)日：2001-01-30

    申请号：US08977728

    申请日：1997-11-25

    申请人： Kuei-Wu Huang ,  Tsiu C. Chan ,  Jamin Ling

    发明人： Kuei-Wu Huang ,  Tsiu C. Chan ,  Jamin Ling

    IPC分类号： H01L214763

    CPC分类号： H01L21/7685 ,  H01L21/76819 ,  H01L21/76841 ,  H01L21/76885

    摘要： A method is provided for forming planar multilevel metallization of a semiconductor integrated circuit, and an integrated circuit formed according to the same. Multilevel metallization is achieved through a planar process at each layer to allow for minimum widths of lines and vias and minimal lateral spacing between lines. Conductive lines and contacts are formed before planarization to further achieve good step coverage. A first metallization layer is formed by depositing aluminum over the integrated circuit, patterning and etching to form metal interconnect lines. Regions of planar insulating material are then formed between the metal lines. Another layer of aluminum is deposited and etched to form metal vias over selected portions of the metal lines. This layer of aluminum is patterned with a reverse pattern of that used to pattern the metal lines. Again, regions of planar insulating material are formed between the metal vias. The process of forming the aluminum lines and vias before planarization is free of voids, provides good step coverage and minimizes electromigration problems.

    摘要翻译： 提供一种用于形成半导体集成电路的平面多层金属化的方法和根据该集成电路形成的集成电路。 通过每层的平面工艺实现多层金属化，以允许线和通孔的最小宽度和线之间的最小横向间隔。 在平坦化之前形成导电线和触点，以进一步实现良好的阶梯覆盖。 第一金属化层通过在集成电路上沉积铝形成，图案化和蚀刻以形成金属互连线。 然后在金属线之间形成平面绝缘材料的区域。 沉积和蚀刻另一层铝，以在金属线的选定部分上形成金属通孔。 该铝层被图案化以用于图案化金属线的反向图案。 再次，平面绝缘材料的区域形成在金属通孔之间。 在平坦化之前形成铝线和通孔的过程没有空隙，提供良好的步骤覆盖和最小化电迁移问题。

    Dual landing pad structure including dielectric pocket
    9.
    发明授权
    Dual landing pad structure including dielectric pocket 失效
    双重着陆垫结构包括电介质袋

    公开(公告)号：US06093963A

    公开(公告)日：2000-07-25

    申请号：US943382

    申请日：1997-10-02

    申请人： Tsiu C. Chan ,  Frank R. Bryant ,  Loi N. Nguyen ,  Artur P. Balasinski

    发明人： Tsiu C. Chan ,  Frank R. Bryant ,  Loi N. Nguyen ,  Artur P. Balasinski

    IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/60 ,  H01L21/768 ,  H01L23/485 ,  H01L23/528 ,  H01L27/11 ,  H01L23/48

    CPC分类号： H01L21/28 ,  H01L21/28525 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/5283 ,  H01L24/03 ,  H01L24/05 ,  H01L27/11 ,  H01L2224/05558 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/3011

    摘要： A dual landing pad structure is formed with a dielectric pocket. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A first polysilicon landing pad is formed over the first dielectric layer and in the opening. This landing pad will provide for smaller geometries and meet stringent design rules such as that for contact space to gate. A dielectric pocket is formed over the polysilicon landing pad over the active region. A second conductive landing pad is formed over the polysilicon landing pad and the dielectric pocket. A second dielectric layer is formed over the landing pad having a second opening therethrough exposing a portion of the landing pad. A conductive contact, such as aluminum, is formed in the second contact opening. The conductive contact will electrically connect with the diffused region through the landing pad. Misalignment of the conductive contact opening over the landing pad may be tolerated without invading design rules. The landing pad and the dielectric pocket will enhance planarization to provide for better step coverage of the metal contact in the second opening.

    摘要翻译： 形成具有电介质袋的双重着陆垫结构。 通过第一介电层形成第一开口以暴露扩散区域的一部分。 在第一介电层上和开口中形成第一多晶硅着陆焊盘。 该着陆垫将提供更小的几何形状，并满足严格的设计规则，例如接触空间到门。 在有源区上方的多晶硅着陆垫上形成电介质袋。 在多晶硅着陆焊盘和电介质槽上方形成第二导电焊盘。 第二电介质层形成在着陆焊盘上，具有通过其暴露出一部分着陆焊盘的第二开口。 在第二接触开口中形成诸如铝的导电接触。 导电触点将通过着陆焊盘与扩散区域电连接。 可以容忍在着陆垫上的导电接触开口的不对准，而不会侵入设计规则。 着陆垫和电介质袋将增强平面化，以提供第二开口中的金属接触件的更好的台阶覆盖。

    Field effect device with polycrystalline silicon channel
    10.
    发明授权
    Field effect device with polycrystalline silicon channel 失效
    具多晶硅通道的场效应器件

    公开(公告)号：US5770892A

    公开(公告)日：1998-06-23

    申请号：US460494

    申请日：1995-06-02

    申请人： Tsiu C. Chan ,  Yu-Pin Han ,  Elmer H. Guritz

    发明人： Tsiu C. Chan ,  Yu-Pin Han ,  Elmer H. Guritz

    IPC分类号： H01L21/02 ,  H01L21/8244 ,  H01L27/06 ,  H01L27/11

    CPC分类号： H01L28/20 ,  H01L27/0605 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1108

    摘要： A CMOS SRAM cell has a polycrystalline silicon signal line between a common node, which is the data storage node, and the power supply. A field effect device is fabricated within this polycrystalline silicon signal line. The channel of the field effect device is separated from an active region in the substrate by a thin gate dielectric, and the active region within the substrate functions as the control gate for the field effect device. Such a device can be used to provide polycrystalline silicon P-channel transistors for use in CMOS SRAM cells.

    摘要翻译： CMOS SRAM单元在作为数据存储节点的公共节点和电源之间具有多晶硅信号线。 在该多晶硅信号线内制造场效应器件。 场效应器件的沟道通过薄栅极介质与衬底中的有源区域分离，衬底内的有源区域用作场效应器件的控制栅极。 这种器件可用于提供用于CMOS SRAM单元的多晶硅P沟道晶体管。