公开(公告)号：US20050014326A1

公开(公告)日：2005-01-20

申请号：US10899119

申请日：2004-07-27

申请人： Takashi Kobayashi ,  Yasushi Goto ,  Tokuo Kure ,  Hideaki Kurata ,  Hitoshi Kume ,  Katsutaka Kimura ,  Syunichi Saeki

发明人： Takashi Kobayashi ,  Yasushi Goto ,  Tokuo Kure ,  Hideaki Kurata ,  Hitoshi Kume ,  Katsutaka Kimura ,  Syunichi Saeki

IPC分类号： H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42328 ,  H01L29/7881

摘要： A semiconductor integrated circuit device with third gates comprising second conduction type source/drain diffusion layer regions 205 formed first conduction type well 201, floating gates 203b formed on semiconductor substrate 200 through an insulator film 202, control gates 211a formed on floating gates 203b through nitrogen-introduced silicon oxide film 210a and third gates 207a different from the floating gates and the control gates, formed through the semiconductor substrates, the floating gates, the control gates and the insulator film, where the third gates are formed as filled in gaps between the floating gates existing in a vertical direction to word lines and channels and the height of third gates 207a thus formed is made lower than that of floating gates 203b, has improved reduction of memory cell size and operating speed and improved reliability after programming/erasing cycles.

摘要翻译： 具有第三栅极的半导体集成电路器件包括形成在第一导电型阱201的第二导电型源极/漏极扩散层区域205，通过绝缘膜202形成在半导体衬底200上的浮动栅极203b，通过氮气形成在浮动栅极203b上的控制栅极211a 引入与通过半导体衬底，浮动栅极，控制栅极和绝缘膜形成的浮动栅极和控制栅极不同的氧化硅膜210a和第三栅极207a，其中第三栅极形成为填充在第 存在于字线和沟道的垂直方向的浮动栅极和由此形成的第三栅极207a的高度低于浮置栅极203b的高度，改善了编程/擦除周期后存储单元尺寸和操作速度的降低以及改进的可靠性。

公开(公告)号：USRE38296E1

公开(公告)日：2003-11-04

申请号：US08408788

申请日：1995-03-23

申请人： Noboru Moriuchi ,  Yoshiki Yamaguchi ,  Toshihiko Tanaka ,  Norio Hasegawa ,  Yoshifumi Kawamoto ,  Shin-ichiro Kimura ,  Toru Kaga ,  Tokuo Kure

发明人： Noboru Moriuchi ,  Yoshiki Yamaguchi ,  Toshihiko Tanaka ,  Norio Hasegawa ,  Yoshifumi Kawamoto ,  Shin-ichiro Kimura ,  Toru Kaga ,  Tokuo Kure

IPC分类号： H01L27108

CPC分类号： H01L27/10808 ,  H01L27/105 ,  H01L27/10852

摘要： A semiconductor memory wherein a memory cell region having a plurality of memory cells and a relatively high altitude above the surface of semiconductor substrate is formed at a recessed part of the semiconductor substrate having the recessed part and a projected part, and wherein a peripheral circuit region having a comparatively low altitude from the surface of the semiconductor substrate is formed at the projected part of the semiconductor substrate.

公开(公告)号：US6114695A

公开(公告)日：2000-09-05

申请号：US307789

申请日：1999-05-10

申请人： Hideo Todokoro ,  Kenji Takamoto ,  Tadashi Otaka ,  Fumio Mizuno ,  Satoru Yamada ,  Sadao Terakado ,  Katsuhiro Kuroda ,  Ken Ninomiya ,  Tokuo Kure

发明人： Hideo Todokoro ,  Kenji Takamoto ,  Tadashi Otaka ,  Fumio Mizuno ,  Satoru Yamada ,  Sadao Terakado ,  Katsuhiro Kuroda ,  Ken Ninomiya ,  Tokuo Kure

IPC分类号： G01Q30/02 ,  G01B15/00 ,  G01B15/04 ,  G01Q30/04 ,  H01J37/26

CPC分类号： G01B15/00 ,  G01B15/04 ,  H01J2237/2448 ,  H01J2237/24495 ,  H01J2237/281

摘要： An electron beam which can transmit through part of a specimen and can reach a portion not exposing to the electron beam is irradiated and a scanning image is obtained on the basis of a signal secondarily generated from a portion irradiated with the electron beam. Dimension-measuring start and end points are set on the scanning image and a dimension therebetween is measured. A cubic model is assumed, the cubic model is modified so as to match the scanning image, and dimension measurement is carried out on the basis of a modified cubic model.

摘要翻译： 照射可以透过部分试样并且可以到达不暴露于电子束的部分的电子束，并且基于从照射电子束的部分二次产生的信号获得扫描图像。 在扫描图像上设置尺寸测量开始点和终点，并测量它们之间的尺寸。 假设立方模型，修改立方体模型以匹配扫描图像，并且基于修改的立方体模型进行尺寸测量。

公开(公告)号：US5412210A

公开(公告)日：1995-05-02

申请号：US160336

申请日：1993-12-02

申请人： Hideo Todokoro ,  Kenji Takamoto ,  Tadashi Otaka ,  Fumio Mizuno ,  Satoru Yamada ,  Katsuhiro Kuroda ,  Ken Ninomiya ,  Tokuo Kure

发明人： Hideo Todokoro ,  Kenji Takamoto ,  Tadashi Otaka ,  Fumio Mizuno ,  Satoru Yamada ,  Katsuhiro Kuroda ,  Ken Ninomiya ,  Tokuo Kure

IPC分类号： G01B15/04 ,  G01Q30/02 ,  G01Q30/04 ,  G01Q30/12 ,  G01Q30/16 ,  G01Q30/18 ,  G01Q70/00 ,  H01J37/28 ,  H01J37/30 ,  H01J37/26

CPC分类号： G01B15/04 ,  H01J37/28 ,  H01J37/3005 ,  H01J2237/226 ,  H01J2237/2448 ,  H01J2237/24495 ,  H01J2237/281

摘要： A technique for displaying a scanned specimen image permits non-destructive observation of a surface structure having large or precipitous unevenness, an internal structure of a specimen or a specific structure of a defect or foreign matter, which non-destructive observation has hitherto been considered to be difficult to achieve. The technique can be applied to inspection and measurement so as to economically provide devices and parts of high quality and high reliability. Thus, secondary information such as secondary electrons resulting from interaction of primary information with a specimen, the primary information being generated as a result of interaction of a scanning electron beam with the specimen, is utilized as an image signal to form an image.

摘要翻译： 用于显示扫描的样本图像的技术允许对具有大的或陡峭的不均匀性，样本的内部结构或缺陷或异物的特定结构的表面结构进行非破坏性观察，迄今为止已经认为非破坏性观察 难以实现。 该技术可以应用于检测和测量，从而经济地提供高质量和高可靠性的设备和部件。 因此，作为图像信号利用作为扫描电子束与样本的相互作用的结果而生成的主要信息的次要信息，例如由主要信息与样本的相互作用产生的二次电子。

公开(公告)号：US5196910A

公开(公告)日：1993-03-23

申请号：US650999

申请日：1991-02-04

申请人： Noboru Moriuchi ,  Yoshiki Yamaguchi ,  Toshihiko Tanaka ,  Norio Hasegawa ,  Yoshifumi Kawamoto ,  Shin-ichiro Kimura ,  Toru Kaga ,  Tokuo Kure

发明人： Noboru Moriuchi ,  Yoshiki Yamaguchi ,  Toshihiko Tanaka ,  Norio Hasegawa ,  Yoshifumi Kawamoto ,  Shin-ichiro Kimura ,  Toru Kaga ,  Tokuo Kure

IPC分类号： H01L21/8242 ,  H01L27/105 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10808 ,  H01L27/105

摘要： A semiconductor memory wherein a memory cell region having a plurality of memory cells and a relatively high altitude above the surface of semiconductor substrate is formed at a recessed part of the semiconductor substrate having the recessed part and a projected part, and wherein a peripheral circuit region having a comparatively low altitude from the surface of the semiconductor substrate is formed at the projected part of the semiconductor substrate.

摘要翻译： 一种半导体存储器，其中具有多个存储单元的存储单元区域和半导体衬底的表面上方相对高的高度形成在具有凹部和突出部分的半导体衬底的凹部中，并且其中外围电路区域 在半导体衬底的突出部分处形成从半导体衬底的表面相对较低的高度。

公开(公告)号：US5177576A

公开(公告)日：1993-01-05

申请号：US695984

申请日：1991-05-06

申请人： Shin'ichiro Kimura ,  Tokuo Kure ,  Toru Kaga ,  Digh Hisamoto ,  Eiji Takeda

发明人： Shin'ichiro Kimura ,  Tokuo Kure ,  Toru Kaga ,  Digh Hisamoto ,  Eiji Takeda

IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10841

摘要： A vertical semiconductor memory device is provided which capable of miniaturization. More particularly, a memory cell is provided having a trench capacitor and a vertical transistor in a dynamic random access memory suitable for high density integration. An object of this arrangement is to provide a vertical memory cell capable of miniaturization for use in a ultra-high density integration DRAM of a Gbit class. This memory cell is characterized in that each memory cell is covered with an oxide film, an impurity area does not exist on the substrate side, an area in which a channel area is formed is a hollow cylindrical single crystal area, connection of impurity areas as source-drain areas and bit lines and the electrode of a capacitor is made by self-alignment and connection between a word line electrode and a gate electrode is also made by self-alignment.

摘要翻译： 提供能够小型化的垂直半导体存储器件。 更具体地说，在动态随机存取存储器中提供具有沟槽电容器和垂直晶体管的存储单元，其适用于高密度集成。 这种布置的目的是提供一种能够小型化的垂直存储单元，用于Gbit级的超高密度集成DRAM。 该存储单元的特征在于，每个存储单元被氧化物膜覆盖，基板侧不存在杂质区域，形成沟道区域的区域是中空圆柱形单晶区域，杂质区域的连接为 源极 - 漏极区域和位线，并且电容器的电极通过自对准而形成，并且字线电极和栅电极之间的连接也通过自对准来进行。

公开(公告)号：US4985114A

公开(公告)日：1991-01-15

申请号：US418223

申请日：1989-10-06

申请人： Sadayuki Okudaira ,  Hiroshi Kawakami ,  Tokuo Kure ,  Kazunori Tsujimoto ,  Shinichi Tachi

发明人： Sadayuki Okudaira ,  Hiroshi Kawakami ,  Tokuo Kure ,  Kazunori Tsujimoto ,  Shinichi Tachi

IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3213

CPC分类号： H01L21/32139 ,  H01L21/30655 ,  H01L21/3085 ,  H01L21/31144 ,  Y10S438/913

摘要： A dry etching method including the steps of introducing etching and deposition gases alternately into a reaction chamber at predetermined time intervals, etching the exposed surface of an article to be etched and applying deposition to the surface film thereof alternately by making plasma generated by applying power to the etching and deposition gases introduced into the reaction chamber come in contact with the article to be etched in the reaction chamber in order to etch the surface, is characterized in that the power is applied after the passage of predetermined time from the start of the introduction of the deposition gas and before the etching gas is introduced and cut off when the introduction of the etching gas is suspended.

公开(公告)号：US4984048A

公开(公告)日：1991-01-08

申请号：US216536

申请日：1988-07-08

申请人： Kazuhiko Sagara ,  Tokuo Kure ,  Eiichi Murakami ,  Tohru Nakamura ,  Masanobu Miyao ,  Masao Kondo ,  Akitoshi Ishizaka ,  Yoichi Tamaki

发明人： Kazuhiko Sagara ,  Tokuo Kure ,  Eiichi Murakami ,  Tohru Nakamura ,  Masanobu Miyao ,  Masao Kondo ,  Akitoshi Ishizaka ,  Yoichi Tamaki

IPC分类号： H01L21/74 ,  H01L21/763 ,  H01L29/06 ,  H01L29/417 ,  H01L29/732 ,  H01L29/737

CPC分类号： H01L29/0649 ,  H01L21/743 ,  H01L21/763 ,  H01L29/41716 ,  H01L29/7325 ,  H01L29/7327 ,  H01L29/7378

摘要： Polycrystalline silicon which is provided within a trench for isolating a plurality of bipolar transistors from each other is electrically connected to the collector of one of the bipolar transistor. Since the trench for isolation can also be used to lead out the collector electrode, the required area is minimized. Thus, the arrangement is effective in creasing the integration density.

摘要翻译： 设置在用于将多个双极晶体管彼此隔离的沟槽内的多晶硅电连接到双极晶体管之一的集电极。 由于用于隔离的沟槽也可以用于引出集电极，因此所需的面积被最小化。 因此，这种布置在增加集成密度方面是有效的。

公开(公告)号：US4984038A

公开(公告)日：1991-01-08

申请号：US194980

申请日：1988-05-17

申请人： Hideo Sunami ,  Makoto Ohkura ,  Masanobu Miyao ,  Kikuo Kusukawa ,  Masahiro Moniwa ,  ShinIchiro Kimura ,  Terunori Warabisako ,  Tokuo Kure

发明人： Hideo Sunami ,  Makoto Ohkura ,  Masanobu Miyao ,  Kikuo Kusukawa ,  Masahiro Moniwa ,  ShinIchiro Kimura ,  Terunori Warabisako ,  Tokuo Kure

IPC分类号： H01L21/762 ,  H01L27/108

CPC分类号： H01L21/762 ,  H01L27/10841

摘要： The side wall part of a recess dug in a Si substrate is used as the major part of the electrode surface of a capacitor, whereby the electrode area is enlarged without enlarging a plane area. Thus, a desired capacitor capacitance can be attained without increasing the breakdown of an insulator film ascribable to the conventional approach of thinning of the insulator film. In addition, a vertical switching transistor is formed on the Si substrate, whereby the Si substrate can be entirely utilized for the formation of the capacitor.

公开(公告)号：US4829361A

公开(公告)日：1989-05-09

申请号：US120921

申请日：1987-11-16

申请人： Kazuhiko Sagara ,  Tohru Nakamura ,  Kazuo Nakazato ,  Tokuo Kure ,  Kiyoji Ikeda ,  Noriyuki Homma

发明人： Kazuhiko Sagara ,  Tohru Nakamura ,  Kazuo Nakazato ,  Tokuo Kure ,  Kiyoji Ikeda ,  Noriyuki Homma

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/74 ,  H01L21/762 ,  H01L21/8229 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/10 ,  H01L27/102 ,  H01L29/732

CPC分类号： H01L27/1025 ,  H01L21/74 ,  H01L21/762 ,  Y10S257/906

摘要： A semiconductor device wherein a layer doped with impurities is provided between a buried layer and an epitaxial layer, said layer doped with impurities having a conductivity of the type opposite to that of said buried layer and said epitaxial layer, a reversely biasing voltage is applied across the buried layer and the layer doped with impurities, and side surfaces of the epitaxial layer are surrounded by an insulator.This helps effectively prevent the element formed in the epitaxial layer from being affected by .alpha.-particles and greatly improve reliability of the semiconductor device.

摘要翻译： 一种半导体器件，其中在掩埋层和外延层之间提供掺杂有杂质的层，所述层掺杂有与所述掩埋层和所述外延层的导电类型相反的导电类型的杂质，施加反向偏置电压 掺杂有杂质的掩埋层和层，外延层的侧表面被绝缘体包围。 这有助于有效地防止外延层中形成的元件受到α-粒子的影响，并且极大地提高了半导体器件的可靠性。