公开(公告)号：US20050064157A1

公开(公告)日：2005-03-24

申请号：US10979428

申请日：2004-11-02

Applicant: Takeshi Okazawa ,  Katsumi Suemitsu

Inventor： Takeshi Okazawa ,  Katsumi Suemitsu

IPC: G11C11/14 ,  G11C11/15 ,  G11C11/56 ,  H01F10/32 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08 ,  B32B7/06

CPC classification number: G11C11/5607 ,  G11C11/15 ,  G11C11/161 ,  Y10T428/2486

Abstract: A magnetic memory according to the present invention comprises: a single magnetic memory cell having at least first to third magnetic layers, a first tunnel insulating layer between the first and second magnetic layers and a second tunnel insulating layer between the second and third magnetic layers. The resistance between the first and third magnetic layers when magnetization of the first and second magnetic layers are in opposite directions is different from the resistance between the second and third magnetic layers when magnetization of the second and third magnetic layers are in opposite directions. Multiple data are therefore stored into the memory cell.

Abstract translation: 根据本发明的磁存储器包括：具有至少第一至第三磁性层的单个磁存储单元，在第一和第二磁性层之间的第一隧道绝缘层以及第二和第三磁性层之间的第二隧道绝缘层。 当第一和第二磁性层的磁化方向处于相反方向时，第一和第三磁性层之间的电阻不同于当第二和第三磁性层的磁化方向相反时第二和第三磁性层之间的电阻。 因此，多个数据被存储到存储单元中。

公开(公告)号：US06834018B2

公开(公告)日：2004-12-21

申请号：US10291216

申请日：2002-11-08

Applicant: Takeshi Okazawa ,  Shuuichi Tahara

Inventor： Takeshi Okazawa ,  Shuuichi Tahara

IPC: G11C702

CPC classification number: G11C11/16

Abstract: A semiconductor memory device as claimed in the present invention has a reference cell, a first memory cell, a second memory cell located nearer the first memory cell than the reference cell and a data read circuit provided therein. The data read circuit identifies first data stored in the first memory cell based on a reference cell electrical state of the reference cell and a first electrical state of the first memory cell. Furthermore, the data read circuit identifies second data stored in the second memory cell based on the first electrical state of the first memory cell and a second electrical state of the second memory cell. The semiconductor memory device having such configuration is able to suppress influence of variation in electrical performance of memory cell and stably identify data stored in a memory cell.

Abstract translation: 本发明的半导体存储器件具有比参考单元更靠近第一存储单元的参考单元，第一存储单元，第二存储器单元和设置在其中的数据读取电路。 数据读取电路基于参考单元的参考单元电状态和第一存储单元的第一电状态来识别存储在第一存储器单元中的第一数据。 此外，数据读取电路基于第一存储单元的第一电状态和第二存储单元的第二电状态来识别存储在第二存储单元中的第二数据。 具有这种结构的半导体存储器件能够抑制存储单元的电气性能变化的影响，并且可以稳定地识别存储在存储单元中的数据。

公开(公告)号：US06812537B2

公开(公告)日：2004-11-02

申请号：US10141602

申请日：2002-05-08

Applicant: Takeshi Okazawa ,  Katsumi Suemitsu

Inventor： Takeshi Okazawa ,  Katsumi Suemitsu

IPC: H01L2982

CPC classification number: G11C11/5607 ,  G11C11/15 ,  Y10T428/2486

Abstract: A magnetic memory according to the present invention comprises: a single magnetic memory cell having at least first to third magnetic layers, a first tunnel insulating layer between the first and second magnetic layers and a second tunnel insulating layer between the second and third magnetic layers. The resistance between the first and third magnetic layers when magnetization of the first and second magnetic layers are in opposite directions is different from the resistance between the second and third magnetic layers when magnetization of the second and third magnetic layers are in opposite directions. Multiple data are therefore stored into the memory cell.

Abstract translation: 根据本发明的磁存储器包括：具有至少第一至第三磁性层的单个磁存储单元，在第一和第二磁性层之间的第一隧道绝缘层以及第二和第三磁性层之间的第二隧道绝缘层。 当第一和第二磁性层的磁化方向处于相反方向时，第一和第三磁性层之间的电阻不同于当第二和第三磁性层的磁化方向相反时第二和第三磁性层之间的电阻。 因此，多个数据被存储到存储单元中。

公开(公告)号：US5309402A

公开(公告)日：1994-05-03

申请号：US835357

申请日：1992-02-14

Applicant: Takeshi Okazawa

Inventor： Takeshi Okazawa

IPC: G11C16/16 ,  H01L21/8247 ,  H01L27/115 ,  G11C11/40

CPC classification number: H01L27/11517 ,  G11C16/16 ,  H01L27/115

Abstract: A flash EEPROM with sector erasure, carries out the erasure by applying a negative voltage to a selected word line through an N-channel MOS transistor. P-channel MOS transistors are respectively inserted between row decoder level shifters and each of their respective word lines to which they are respectively connected. The turning-on and -off of the respective word lines and first level shifters is controlled by the turning-on and -off of the associated P-channel MOS transistor. An erase voltage is applied to one end of the source/drain path of the respective N-channel MOS transistor of the selected cord line, the other end to the respective word lines. The turning-on and -off of the N-channel MOS transistor is synchronized with the turning-on and -off of the P-channel MOS transistor connected to the same word line. The P-channel MOS transistor is formed on an N well biased to, for example, 5 V and the N-channel MOS transistor is formed on a P well biased to, for example, the erase voltage. The P well is formed on the surface of the N well.

Abstract translation: 具有扇区擦除的快闪EEPROM通过通过N沟道MOS晶体管对所选字线施加负电压来执行擦除。 P沟道MOS晶体管分别插入在行解码器电平移位器和它们各自连接的各自的字线之间。 各个字线和第一电平移位器的导通和关断由相关的P沟道MOS晶体管的导通和关断来控制。 擦除电压被施加到所选择的线路的各个N沟道MOS晶体管的源极/漏极路径的一端，另一端被施加到各个字线。 N沟道MOS晶体管的导通和关断与连接到同一字线的P沟道MOS晶体管的导通和关断同步。 P沟道MOS晶体管形成在N阱上，例如被偏压到5V，并且N沟道MOS晶体管形成在P偏置到例如擦除电压的P上。 P井形成在N井的表面上。

公开(公告)号：US5295107A

公开(公告)日：1994-03-15

申请号：US24074

申请日：1993-03-01

Applicant: Takeshi Okazawa ,  Ken-Ichi Oyama ,  Hiroki Shirai

Inventor： Takeshi Okazawa ,  Ken-Ichi Oyama ,  Hiroki Shirai

IPC: G11C17/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/16 ,  H01L21/8247 ,  H01L27/115 ,  G11C7/00

CPC classification number: G11C16/3409 ,  G11C16/16

Abstract: A method of controlling the nonvolatile memory device comprising making over-erasing simultaneously a set of EEPROM elements and then setting simultaneously the threshold voltages of said set of EEPROM elements back to the specified threshold-voltage values. The over-erasing is accomplished by applying a first pulse between the source and the control gate to induce the first FN current across the gate insulating film. The setting-back is accomplished by applying a second pulse between the well and the control gate to induce the second FN current flowing reversely to the first FN current.

Abstract translation: 一种控制非易失性存储器件的方法，包括同时进行一组EEPROM元件的过度擦除，然后同时将所述EEPROM元件组的阈值电压恢复到指定的阈值电压值。 通过在源极和控制栅极之间施加第一脉冲以引导跨越栅极绝缘膜的第一FN电流来实现过擦除。 通过在阱和控制栅之间施加第二脉冲以引起与第一FN电流相反流动的第二FN电流来实现回调。

公开(公告)号：US07405958B2

公开(公告)日：2008-07-29

申请号：US10464010

申请日：2003-06-18

Applicant: Takeshi Okazawa

Inventor： Takeshi Okazawa

IPC: G11C5/08 ,  G11C11/00 ,  G11C8/00 ,  G11C8/02

CPC classification number: G11C11/005 ,  G11C11/16

Abstract: According to the semiconductor memory device of this invention, an XP type MRAM cell array and an STr type MRAM cell array are formed on a single chip. The XP type MRAM cell array is laid over the STr type MRAM cell array to form a layered structure. The STr type MRAM cell array serves as a work memory area, while the XP type MRAM cell array serves as a data storage area. A cell of the XP type MRAM cell array and a cell of the STr type MRAM cell array may be connected to a same bit-line. By passing predetermined current through the bit-line, and passing current through a first word-line connected to the cell of the XP type MRAM cell array, and through a second word-line connected to the cell of the STr type MRAM cell array, it is possible to simultaneously write data into the cells of the XP and STr type MRAM cell arrays.

Abstract translation: 根据本发明的半导体存储器件，在单个芯片上形成XP型MRAM单元阵列和STr型MRAM单元阵列。 XP型MRAM单元阵列放置在STr型MRAM单元阵列上以形成分层结构。 STR型MRAM单元阵列用作工作存储器区域，而XP型MRAM单元阵列用作数据存储区域。 XP型MRAM单元阵列的单元和STr型MRAM单元阵列的单元可以连接到相同的位线。 通过使预定电流通过位线，并且使电流通过连接到XP型MRAM单元阵列的单元的第一字线，并通过连接到STr型MRAM单元阵列的单元的第二字线， 可以将数据同时写入XP和STr型MRAM单元阵列的单元格中。

公开(公告)号：US06643168B2

公开(公告)日：2003-11-04

申请号：US10067864

申请日：2002-02-08

Applicant: Takeshi Okazawa

Inventor： Takeshi Okazawa

IPC: G11C1115

CPC classification number: H01L27/228 ,  G11C11/16

Abstract: A magnetic memory device of the present invention includes a first wiring conductor having a first ability to flow a current therethrough, a second wiring conductor having a second ability larger than the first ability to flow a current therethrough, a magnetic memory cell having a pinned magnetic layer coupled to the second wiring conductor, a free magnetic layer coupled to the first wiring conductor and anon-magnetic layer sandwiched between the first and second magnetic layers. The first wiring conductor is made by aluminum and the second wiring conductor is made by copper.

公开(公告)号：US06532163B2

公开(公告)日：2003-03-11

申请号：US09954267

申请日：2001-09-18

Applicant: Takeshi Okazawa

Inventor： Takeshi Okazawa

IPC: G11C1115

CPC classification number: G11C11/15

Abstract: The present invention provides a memory cell array structure comprising: a plurality of cell array blocks aligned in matrix in both the row and column directions, and each of the cell array blocks including a plurality of magnetic memory cells; a plurality of main word lines being connected through sub-word switching devices to the same number of sub-word lines as a first number of the cell array blocks aligned in the row direction, and each of the sub-word lines being connected to at least one of the magnetic memory cells; and a plurality of main bit lines being connected through sub-bit switching devices to the same number of sub-bit lines as a second number of the cell array blocks aligned in the column direction, and each of the sub-bit lines being connected to at least one of the magnetic memory cells.

Abstract translation: 本发明提供一种存储单元阵列结构，包括：在行和列方向上以矩阵排列的多个单元阵列块，每个单元阵列块包括多个磁存储单元; 多个主字线通过子字切换装置连接到与行方向对齐的第一数量的单元阵列块相同数量的子字线，并且每个子字线连接到 磁记录单元中的至少一个; 并且多个主位线通过子位开关器件连接到与在列方向上排列的第二数量的单元阵列块相同数量的子位线，并且每个子位线被连接到 至少一个磁存储单元。

公开(公告)号：US5787036A

公开(公告)日：1998-07-28

申请号：US764362

申请日：1996-12-12

Applicant: Takeshi Okazawa

Inventor： Takeshi Okazawa

IPC: H01L21/8247 ,  G11C11/56 ,  G11C16/04 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/02

CPC classification number: G11C11/5628 ,  G11C11/5621 ,  G11C16/0416 ,  H01L29/7887

Abstract: A flash memory includes a plurality of MOSFETs. Each of the MOSFETs comprises a first conductive type substrate, a source, and a drain. The source and the drain are formed on one major surface of the substrate. A floating gate is situated over the major surface via a first insulation layer in a manner to control a current flowing through a channel between the source and the drain. The floating gate is highly resistive so as to essentially hold electrons in the region into which they were are injected from a depletion layer formed in the channel. A control gate is further provided over the floating gate via a second insulation layer.

Abstract translation: 闪存包括多个MOSFET。 每个MOSFET包括第一导电类型的衬底，源极和漏极。 源极和漏极形成在衬底的一个主表面上。 浮动栅极通过第一绝缘层位于主表面上方，以控制流过源极和漏极之间的沟道的电流。 浮置栅极具有高电阻性，从而在形成于通道中的耗尽层基本上将电子注入到其中注入的区域。 控制栅极还经由第二绝缘层设置在浮栅上。

公开(公告)号：US5523976A

公开(公告)日：1996-06-04

申请号：US388453

申请日：1995-02-14

Applicant: Takeshi Okazawa ,  Kenji Saitoh

Inventor： Takeshi Okazawa ,  Kenji Saitoh

IPC: G11C17/00 ,  G11C16/04 ,  G11C16/06 ,  G11C29/00 ,  G11C29/04 ,  H01L21/8247 ,  H01L27/115 ,  G11C7/00

CPC classification number: G11C29/808 ,  G11C29/82

Abstract: A plurality of semiconductor memory cells are arranged in the form of a matrix and capable of electrically erasing and re-programming. Each of word lines is provided commonly to the memory cells in each row of the matrix and commonly connected to the gates of these memory cells, and each of bit lines is provided commonly to the memory cells in each column of the matrix and commonly connected to the drains of these memory cells. Each of common source lines is commonly connected to the sources of the memory cells in each pair of adjacent rows of the matrix. A memory cell group in a predetermined row or row pair of the matrix is operative as a redundant memory cell group for replacement of the other group.

Abstract translation: 多个半导体存储单元以矩阵的形式布置，并且能够电擦除和重新编程。 每个字线被共同地提供给矩阵的每一行中的存储器单元，并且通常连接到这些存储器单元的栅极，并且每个位线被共同地提供给矩阵的每列中的存储器单元，并且通常连接到 这些记忆单元的下水道。 每个公共源极线通常连接到矩阵的每对相邻行中的存储器单元的源极。 矩阵的预定行或行对中的存储单元组可用作用于替换另一组的冗余存储单元组。