A flash EEPROM with sector erasure, carries out the erasure by applying a negative voltage to a selected word line through an N-channel MOS transistor. P-channel MOS transistors are respectively inserted between row decoder level shifters and each of their respective word lines to which they are respectively connected. The turning-on and -off of the respective word lines and first level shifters is controlled by the turning-on and -off of the associated P-channel MOS transistor. An erase voltage is applied to one end of the source/drain path of the respective N-channel MOS transistor of the selected cord line, the other end to the respective word lines. The turning-on and -off of the N-channel MOS transistor is synchronized with the turning-on and -off of the P-channel MOS transistor connected to the same word line. The P-channel MOS transistor is formed on an N well biased to, for example, 5 V and the N-channel MOS transistor is formed on a P well biased to, for example, the erase voltage. The P well is formed on the surface of the N well.