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公开(公告)号：US09048180B2
公开(公告)日：2015-06-02
申请号：US11383721
申请日：2006-05-16
IPC分类号： H01L21/02 , H01L21/265 , H01L21/318 , H01L21/324 , H01L29/66
CPC分类号： H01L21/26513 , H01L21/3185 , H01L21/324 , H01L29/6656 , H01L29/6659
摘要： A low stress sacrificial cap layer 120 having a silicon oxide liner film 130, a low stress silicon film 140, and a silicon nitride film Alternatively, a low stress sacrificial cap layer 410 having a silicon oxide liner film 130 and a graded silicon nitride film 420. Also, methods 300, 500 for fabricating a transistor 20, 400 having a low stress sacrificial cap layer 120, 410.
摘要翻译： 具有氧化硅衬垫膜130，低应力硅膜140和氮化硅膜的低应力牺牲帽层120或者，具有氧化硅衬垫膜130和梯度氮化硅膜420的低应力牺牲帽层410 而且，用于制造具有低应力牺牲帽层120,410的晶体管20,400的方法300,500。
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公开(公告)号：US20090170256A1
公开(公告)日：2009-07-02
申请号：US12206456
申请日：2008-09-08
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L21/268 , H01L21/2686 , H01L21/324 , H01L21/823807 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A method of forming a transistor comprising forming a gate structure over an n-type semiconductor body and forming recesses substantially aligned to the gate structure in the semiconductor body. Silicon germanium is then epitaxially grown in the recesses and a silicon cap layer is formed over the silicon germanium. Further introduction of impurities into the silicon germanium to increase the melting point thereof and implanting p-type source/drain regions in the semiconductor body is included in the method. The method concludes with performing a high temperature thermal treatment.
摘要翻译： 一种形成晶体管的方法，包括在n型半导体本体上形成栅极结构，并形成与半导体本体中的栅极结构基本对准的凹槽。 然后在凹槽中外延生长硅锗，并在硅锗上形成硅帽层。 在该方法中包括将杂质进一步引入硅锗以增加其熔点并在半导体本体中注入p型源/漏区。 该方法的结论是进行高温热处理。
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公开(公告)号：US20090045472A1
公开(公告)日：2009-02-19
申请号：US11837709
申请日：2007-08-13
申请人： Srinivasan Chakravarthi , Narendra Singh Mehta , Rajesh Khamankar , Ajith Varghese , Malcolm J. Bevan , Tad Grider
发明人： Srinivasan Chakravarthi , Narendra Singh Mehta , Rajesh Khamankar , Ajith Varghese , Malcolm J. Bevan , Tad Grider
IPC分类号： H01L29/94 , H01L21/8234
CPC分类号： H01L21/26506 , H01L21/2658 , H01L21/28035 , H01L21/28176 , H01L29/4916 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device includes source/drain regions formed in a substrate and having a concentration of nitrogen of at least about 5E18 cm−3. A gate dielectric is located over the substrate and between the source/drain regions. Gate sidewall spacers are located over said source/drain regions. A nitrogen-doped electrode including polysilicon is located over the gate dielectric. The electrode has a concentration of nitrogen therein greater than the concentration of nitrogen in the source/drain regions.
摘要翻译： 半导体器件包括形成在衬底中并具有至少约5E18cm-3的氮浓度的源极/漏极区域。 栅极电介质位于衬底上并且在源/漏区之间。 栅极侧壁间隔物位于所述源极/漏极区域之上。 包括多晶硅的氮掺杂电极位于栅极电介质上方。 电极的氮浓度大于源极/漏极区域中的氮浓度。
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公开(公告)号：US20080277699A1
公开(公告)日：2008-11-13
申请号：US11747708
申请日：2007-05-11
IPC分类号： H01L29/94 , H01L21/336
CPC分类号： H01L29/7848 , H01L21/3065 , H01L29/165 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7834
摘要： A PMOS transistor and a method for fabricating a PMOS transistor. The method may include providing a semiconductor wafer having a PMOS transistor gate stack, source/drain extension regions, and active regions. The method may also include forming epi sidewalls, performing a ex-situ recess etch, and performing an in-situ recess etch. The ex-situ recess etch and the in-situ recess etch form recessed active regions. The PMOS transistor is formed by a method using ex-situ and in-situ etch and has epitaxial SiGe regions with a greatest width at the surface of the semiconductor wafer.
摘要翻译： 一种PMOS晶体管及其制造方法。 该方法可以包括提供具有PMOS晶体管栅极叠层，源极/漏极延伸区域和有源区域的半导体晶片。 该方法还可以包括形成外壁侧壁，执行非原位凹槽蚀刻以及进行原位凹槽蚀刻。 原位凹槽蚀刻和原位凹陷蚀刻形成凹陷的有源区。 PMOS晶体管通过使用非原位和原位蚀刻的方法形成，并且具有在半导体晶片的表面处具有最大宽度的外延SiGe区域。
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公开(公告)号：US07112516B2
公开(公告)日：2006-09-26
申请号：US10677614
申请日：2003-10-02
IPC分类号： H01L21/22
CPC分类号： H01L21/2255
摘要： One aspect of the invention relates to a method of forming P-N junctions within a semiconductor substrate. The method involves providing a temporary impurity species, such as fluorine, within the semiconductor crystal matrix prior to solid source in-diffusion of the primary dopant, such as boron. The impurity atom is a faster diffusing species relative to silicon atoms. During in-diffusion, the temporary impurity species acts to reduce the depth to which the primary dopant diffuses and thereby facilitates the formation of very shallow junctions.
摘要翻译： 本发明的一个方面涉及一种在半导体衬底内形成P-N结的方法。 该方法包括在主要掺杂剂例如硼的固体源扩散之前在半导体晶体矩阵内提供临时杂质物质，例如氟。 杂质原子相对于硅原子是更快的扩散物质。 在扩散期间，临时杂质物质用于减小初级掺杂剂扩散的深度，从而有助于形成非常浅的结。
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公开(公告)号：US20050224874A1
公开(公告)日：2005-10-13
申请号：US11148805
申请日：2005-06-09
IPC分类号： H01L21/265 , H01L21/336 , H01L21/425 , H01L29/10 , H01L29/78
CPC分类号： H01L29/6653 , H01L21/26586 , H01L29/1083 , H01L29/6659 , H01L29/7833 , Y10S438/91
摘要： A method of forming a retrograde well in a transistor is provided. A transistor structure having a substrate, a gate, and a gate oxide layer between the substrate and the gate is formed. The substrate includes a channel region located generally below the gate. A first dopant is implanted into the channel region. A second dopant is implanted into the substrate to form a doped source region and a doped drain region. A third dopant is implanted into the gate oxide layer. A source/drain anneal is performed to form a source and a drain in the doped source region and the doped drain region, respectively. The source/drain anneal causes a portion of the first dopant in the channel region to be attracted by the third dopant into the gate oxide layer.
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7.发明申请Interface improvement by stress application during oxide growth through use of backside films 有权通过使用背面薄膜在氧化物生长期间的应力应用的界面改善公开(公告)号：US20050208776A1
公开(公告)日：2005-09-22
申请号：US11083912
申请日：2005-03-18
IPC分类号： H01L21/28 , H01L21/316 , H01L21/318 , H01L21/469 , H01L21/8234 , H01L21/8238 , H01L29/78
CPC分类号： H01L29/7842 , H01L21/0217 , H01L21/02211 , H01L21/02233 , H01L21/02255 , H01L21/02274 , H01L21/28211 , H01L21/31662 , H01L21/3185 , H01L21/823462 , H01L21/823857 , H01L29/7833
摘要： The present invention provides, in one aspect, a method of fabricating a gate oxide layer on a microelectronics substrate. This embodiment comprises forming a stress inducing pattern on a backside of a microelectronics wafer and growing a gate oxide layer on a front side of the microelectronics wafer in the presence of a tensile stress caused by the stress inducing pattern.
摘要翻译： 本发明在一个方面提供了一种在微电子衬底上制造栅氧化层的方法。 该实施例包括在微电子晶片的背面上形成应力诱导图案，并且在由应力诱导图案引起的拉伸应力的存在下，在微电子晶片的正面上生长栅极氧化物层。
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8.发明授权公开(公告)号：US06797593B2
公开(公告)日：2004-09-28
申请号：US10243610
申请日：2002-09-13
申请人： Srinivasan Chakravarthi , Amitabh Jain , Xin Zhang
发明人： Srinivasan Chakravarthi , Amitabh Jain , Xin Zhang
IPC分类号： H01L21425
CPC分类号： H01L29/6653 , H01L21/26513 , H01L21/324 , H01L29/665 , H01L29/6659
摘要： Methods are described for fabricating MOS type transistors, in which multiple drain extension implants are performed using different dopant species of the same type. The implanted drain extension dopants are activated using separate anneal processes to provide active dopants of both species throughout the drain extension regions adjacent the transistor channel.
摘要翻译： 描述了用于制造MOS型晶体管的方法，其中使用相同类型的不同掺杂剂种类来执行多个漏极延伸注入。 注入的漏极延伸掺杂剂使用单独的退火工艺来激活，以在与晶体管沟道相邻的漏极延伸区域提供两种物质的有源掺杂剂。
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公开(公告)号：US07994073B2
公开(公告)日：2011-08-09
申请号：US11940433
申请日：2007-11-15
IPC分类号： H01L21/31
CPC分类号： H01L21/26513 , H01L21/3185 , H01L21/324 , H01L29/6656 , H01L29/6659
摘要： A low stress sacrificial cap layer 120 having a silicon oxide liner film 130, a low stress silicon film 140, and a silicon nitride film. Alternatively, a low stress sacrificial cap layer 410 having a silicon oxide liner film 130 and a graded silicon nitride film 420. Also, methods 300, 500 for fabricating a transistor 20, 400 having a low stress sacrificial cap layer 120, 410.
摘要翻译： 具有氧化硅衬垫膜130，低应力硅膜140和氮化硅膜的低应力牺牲帽层120。 或者，具有氧化硅衬垫膜130和梯度氮化硅膜420的低应力牺牲帽层410.而且，用于制造具有低应力牺牲帽层120,410的晶体管40,400的方法300,500。
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公开(公告)号：US20090179236A1
公开(公告)日：2009-07-16
申请号：US12407636
申请日：2009-03-19
IPC分类号： H01L29/772
CPC分类号： H01L29/7848 , H01L21/3065 , H01L29/165 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7834
摘要： A PMOS transistor and a method for fabricating a PMOS transistor. The method may include providing a semiconductor wafer having a PMOS transistor gate stack, source/drain extension regions, and active regions. The method may also include forming epi sidewalls, performing a ex-situ recess etch, and performing an in-situ recess etch. The ex-situ recess etch and the in-situ recess etch form recessed active regions. The PMOS transistor is formed by a method using ex-situ and in-situ etch and has epitaxial SiGe regions with a greatest width at the surface of the semiconductor wafer.
摘要翻译： 一种PMOS晶体管及其制造方法。 该方法可以包括提供具有PMOS晶体管栅极叠层，源极/漏极延伸区域和有源区域的半导体晶片。 该方法还可以包括形成外壁侧壁，执行非原位凹槽蚀刻以及进行原位凹槽蚀刻。 原位凹槽蚀刻和原位凹陷蚀刻形成凹陷的有源区。 PMOS晶体管通过使用非原位和原位蚀刻的方法形成，并且在半导体晶片的表面具有最大宽度的外延SiGe区域。
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