-
1.发明授权Electron beam apparatus and method of generating an electron beam irradiation pattern 有权电子束装置和产生电子束照射图案的方法公开(公告)号：US08008622B2
公开(公告)日：2011-08-30
申请号：US12630346
申请日：2009-12-03
Applicant: Ryo Fujita , Haruo Yoda , Kimiaki Ando , Yuji Inoue , Masato Muraki
Inventor： Ryo Fujita , Haruo Yoda , Kimiaki Ando , Yuji Inoue , Masato Muraki
IPC: H01J37/26
CPC classification number: H01J37/3174 , B82Y10/00 , B82Y40/00 , H01J2237/31762 , H01J2237/31769
Abstract: High-contrast exposure is performed by use of a small dose of electron beams, a pattern is formed on a wafer with high accuracy, and high-precision inspection is performed. In pattern formation, proximity effect correction processing is performed. Moreover, exposure of electron beams is performed based on a result of filtering using an inverse characteristic of exposure characteristics of the electron beams. Furthermore, in pattern inspection, electron beams are irradiated based on a result of filtering for obtaining a peripheral region of an edge of the pattern formed.
Abstract translation: 通过使用小剂量的电子束进行高对比度曝光，以高精度在晶片上形成图案，进行高精度检查。 在图案形成中，执行邻近效应校正处理。 此外，基于使用电子束的曝光特性的逆特性的滤波结果来执行电子束的曝光。 此外，在图案检查中，基于滤波结果照射电子束，以获得形成的图案的边缘的周边区域。
-
公开(公告)号：US20060203000A1
公开(公告)日：2006-09-14
申请号：US11365493
申请日：2006-03-02
Applicant: Koyo Katsura , Yasushi Fukunaga , Ryo Fujita , Kazuyoshi Koga , Takehiko Nishida
Inventor： Koyo Katsura , Yasushi Fukunaga , Ryo Fujita , Kazuyoshi Koga , Takehiko Nishida
IPC: G09G5/39
Abstract: A data processing system including: a memory controller; and a memory connected to said memory controller; wherein said memory controller includes a rendering circuit thereby to execute a rendering command generating display data based on graphic data provided after processing a program in a CPU, and stores said display data in said memory.
-
公开(公告)号：US07019751B2
公开(公告)日：2006-03-28
申请号：US10636769
申请日：2003-08-08
Applicant: Koyo Katsura , Yasushi Fukunaga , Ryo Fujita , Kazuyoshi Koga , Takehiko Nishida
Inventor： Koyo Katsura , Yasushi Fukunaga , Ryo Fujita , Kazuyoshi Koga , Takehiko Nishida
IPC: G09G5/39
Abstract: A graphic processing apparatus for generating, display or printing characters and graphic data. A successive column access is used in which a row address is designated for access to a memory and data in different column address within the designated same row address are successively accessed and buffer means for buffering a series of data between an access by a processor and an access to a memory is provided. A program and image information for display are stored in a main memory. A frame buffer and the main memory are integrally configured simply and small in size.
Abstract translation: 一种用于生成，显示或打印字符和图形数据的图形处理装置。 使用连续的列访问，其中指定行地址用于访问存储器，并且连续地访问指定的相同行地址内的不同列地址中的数据，并且缓冲装置用于在处理器的访问和 提供对内存的访问。 用于显示的程序和图像信息存储在主存储器中。 帧缓冲器和主存储器的整体结构简单，体积小。
-
公开(公告)号：US06935774B2
公开(公告)日：2005-08-30
申请号：US10490288
申请日：2002-09-12
Applicant: Kouji Fujii , Junji Satoh , Hitoshi Uchida , Norio Hashimoto , Ryo Fujita
Inventor： Kouji Fujii , Junji Satoh , Hitoshi Uchida , Norio Hashimoto , Ryo Fujita
CPC classification number: G04B37/1486 , G04B37/082 , G04B37/22
Abstract: A wristwatch case (11) and a method of manufacturing the case, the wristwatch case comprising a wristwatch case body (1) made of titanium or stainless steel and a crown pipe (3) fixed to each other, wherein a stem hole (2) corresponding to the crown pipe (3) is formed in the wristwatch case body (1), a small diameter part is formed in the crown pipe (3), and a small diameter part corresponding to the a small diameter part of the crown pipe is formed in the stem hole (2), the method comprising the step of fitting the crown pipe (3) into the stem hole (2) in the wristwatch case body (1) to form a solid phase diffusion joining part at a portion where the small diameter parts thereof are fitted closely to each other, and to form a brazed connection part at a portion other than that where the small diameter parts are fitted closely to each other, whereby a watch external part having excellent corrosion resistance and waterproof and a large number of design variations can be provided.
Abstract translation: 一种手表壳体（11）及其制造方法，所述手表壳体包括由钛或不锈钢制成的手表壳体（1）和彼此固定的冠状管（3），其中，杆孔（2） 对应于表冠管3形成在手表壳体1中，在冠管3中形成有小径部，与冠管的小直径部对应的小径部为 形成在所述杆孔（2）中的方法，所述方法包括将所述胎冠管（3）装配到所述手表壳体（1）中的所述杆孔（2）中的步骤，以在所述固定相扩散接合部分 其小直径部分彼此紧密地配合，并且在小直径部分彼此紧密地配合的部分以外形成钎焊连接部，由此具有优异的耐腐蚀性和防水性的表壳外部部件 设计变更数量c 提供。
-
5.发明授权Semiconductor memory having an arithmetic function and a terminal arrangement for coordinating operation with a higher processor 失效具有算术功能的半导体存储器和用于与较高处理器协调操作的终端装置
公开(公告)号：US6108746A
公开(公告)日：2000-08-22
申请号：US945575
申请日：1997-10-31
Applicant: Ryo Fujita , Mitsuru Soga , Yasuhiro Nakatsuka
Inventor： Ryo Fujita , Mitsuru Soga , Yasuhiro Nakatsuka
CPC classification number: G06T1/60
Abstract: A display apparatus performs pixel density conversion processing, such as enlargement, reduction, and rotation, on an original image and displays a resultant image an image processing apparatus and, more particularly, a processing apparatus, for performing a high-speed filtering operation, such as data interpolation, involving pixel density conversion processing, uses a memory having an arithmetic function for use in the high-speed filtering operation. The apparatus provides a fraction address including a fraction component of an original image that generally does not provide integer coordinates and a semiconductor memory 100 incorporates a memory cell 207 for holding data corresponding to an integer address, arithmetic circuits 202 and 203 for performing interpolation based on the data corresponding to an integer component of the fraction address read from the memory cell and the fraction component, and an address range determining block 216 for determining whether the above-mentioned given fraction address is in the range of addresses of the data held in the memory cell in the above-mentioned semiconductor memory.
Abstract translation: PCT No.PCT / JP96 / 01166 Sec。 371日期1997年10月31日 102（e）1997年10月31日PCT PCT 1996年4月26日PCT公布。 公开号WO96 / 35992 日期：1996年11月14日显示装置对原始图像进行像放大，缩小和旋转等像素密度变换处理，并显示合成图像的图像处理装置，更具体地说，涉及一种处理装置， 涉及像素密度转换处理的诸如数据插值的速度滤波操作使用具有用于高速滤波操作的算术功能的存储器。 该装置提供包括通常不提供整数坐标的原始图像的分数分量的分数地址，并且半导体存储器100包括用于保存对应于整数地址的数据的存储器单元207，用于基于 对应于从存储器单元读取的分数地址的整数分量的数据和分数分量，以及地址范围确定块216，用于确定上述给定分数地址是否在保持在该存储单元中的数据的地址范围内 上述半导体存储器中的存储单元。
-
Patent Agency Ranking6.发明授权
公开(公告)号：US5995439A
公开(公告)日：1999-11-30
申请号：US188367
申请日：1998-11-10
Applicant: Takao Watanabe , Kazushige Ayukawa , Ryo Fujita , Kazumasa Yanagisawa , Hitoshi Tanaka
Inventor： Takao Watanabe , Kazushige Ayukawa , Ryo Fujita , Kazumasa Yanagisawa , Hitoshi Tanaka
CPC classification number: G11C7/02 , G11C7/10 , G11C7/1006 , G11C7/1042 , G11C7/1072 , H01L27/10897
Abstract: A semiconductor IC device is designed using a memory core with a plurality of I/O lines, a transfer circuit module and a logic library which are produced beforehand and stored in a data base. The memory core and a logic circuit are arranged so that their I/O lines extend in the same direction. A transfer circuit including plural stages of switch groups is arranged between the I/O lines of the memory core and the I/O lines of the logic circuit. Switches forming each stage of switch group are formed between the I/O lines of the memory core and the I/O lines of the logic circuit. When one stage of or a small number of stages of switch groups are turned on, the I/O lines of the memory core and the I/O lines of the logic circuit are turned on, thereby forming a desired transfer pattern. The memory core is constructed by the combination of functional modules such as an amplifier module, a bank module and a power supply module. In the bank module are arranged row-system circuits which operate independently of each other and a multiplicity of I/O lines which extend in a bit line direction.
-
公开(公告)号：US5940087A
公开(公告)日：1999-08-17
申请号：US739457
申请日：1996-10-29
Applicant: Koyo Katsura , Yasushi Fukunaga , Ryo Fujita , Kazuyoshi Koga , Takehiko Nishida
Inventor： Koyo Katsura , Yasushi Fukunaga , Ryo Fujita , Kazuyoshi Koga , Takehiko Nishida
Abstract: A graphic processing apparatus for generating, displaying or printing characters and graphic data. A successive column access is used in which a row address is designated for access to a memory and data in different column addresses within the designated same row address are successively accessed and buffer means for buffering a series of data between an access by a processor and an access to a memory is provided. A program and image information for display are stored in a main memory. A frame buffer and the main memory are integrally configured simply and small in size.
-
8.发明授权Graphics display system including parallel graphics processors executing Bresenham's algorithm 失效图形显示系统包括执行Bresenham算法的并行图形处理器
公开(公告)号：US5847715A
公开(公告)日：1998-12-08
申请号：US856081
申请日：1997-05-14
Applicant: Ryo Fujita , Kazuhisa Takami , Mitsuru Soga , Koji Ozawa , Takaharu Morishige , Kazuyoshi Koga
Inventor： Ryo Fujita , Kazuhisa Takami , Mitsuru Soga , Koji Ozawa , Takaharu Morishige , Kazuyoshi Koga
CPC classification number: G06T11/203 , G06T1/20
Abstract: A graphics display system includes a host processor calculating graphic data and providing the graphic data to a graphics processor, and frame memories which store the graphic pixel data and supply display data to display devices. The graphics display system also includes a first register group which stores the graphics data, a second register group which converts and/or stores the data in the first register group, a pixel generator which generates pixels according to the graphic data in the second register group, and a plotter which writes the pixel data generated in the pixel generator in the frame memories. The second register group fetches the data from the first register group when the host processor issues a command for plotting, holds the data previously written by the host processor. At the same time, when the host processor issues a command for plotting, the specified graphic type is written in the graphic processor as well as data calculated based on the first and second register groups.
Abstract translation: 图形显示系统包括主处理器，其计算图形数据并将图形数据提供给图形处理器，以及存储图形像素数据并向显示装置提供显示数据的帧存储器。 图形显示系统还包括存储图形数据的第一寄存器组，在第一寄存器组中转换和/或存储数据的第二寄存器组，根据第二寄存器组中的图形数据生成像素的像素生成器 ，以及将在像素生成器中生成的像素数据写入帧存储器的绘图仪。 当主机处理器发出绘制命令时，第二个寄存器组从第一个寄存器组中获取数据，保存由主机处理器先前写入的数据。 同时，当主机处理器发出绘制命令时，指定的图形类型被写入图形处理器以及基于第一和第二寄存器组计算的数据。
-
9.发明授权Graphics drawing system and method based on a client server system having shared graphics resources 失效基于具有共享图形资源的客户端服务器系统的图形绘制系统和方法
公开(公告)号：US5819077A
公开(公告)日：1998-10-06
申请号：US620225
申请日：1996-03-22
Applicant: Kazuyoshi Koga , Ryo Fujita , Katsunori Suzuki , Shoji Nakamura , Toshiyuki Kuwana , Hideki Fujii
Inventor： Kazuyoshi Koga , Ryo Fujita , Katsunori Suzuki , Shoji Nakamura , Toshiyuki Kuwana , Hideki Fujii
CPC classification number: G06T1/00 , H04L29/06 , G06F3/1454 , H04L67/38
Abstract: A graphics system utilizes the graphics standardization specification PEX for providing high-speed drawing when a client and a server locally operate on the same machine and allow an application to change structure and graphics attributes defined by another application without being aware of the distinction between local and remote cases.
Abstract translation: 图形系统利用图形标准化规范PEX在客户端和服务器本地在同一台机器上运行时提供高速绘图，并允许应用程序更改由另一应用程序定义的结构和图形属性，而不会意识到本地和 远程情况。
-
公开(公告)号：US5581796A
公开(公告)日：1996-12-03
申请号：US164776
申请日：1993-12-10
Applicant: Kazuyoshi Koga , Ryo Fujita , Koyo Katsura , Yasushi Fukunaga , Hideyuki Hara
Inventor： Kazuyoshi Koga , Ryo Fujita , Koyo Katsura , Yasushi Fukunaga , Hideyuki Hara
Abstract: In a case where a graphic image segment of which positional information is defined in a world coordinate system and of which size information is defined in a device coordinate system is developed to be displayed on a multi-window screen, the development processing performance is improved in peripheral portions of the window. A rectangular development area (first development area) associated with the window is expanded with consideration of a size information of a graphic segment so as to obtain a second development area. The second development area is compared with a rectangular area (an existence area) circumscribing a graphic image represented only with positional information of the graphic segment. As a result, whether or not the graphic segment is to be developed is determined. The first development area is reduced with consideration of size information of the graphic segment to produce a third development area. The third development area is compared with the existence area to decide whether or not the clipping operation is necessary for the graphic segment.
Abstract translation: 在世界坐标系中定义哪个位置信息的图形图像段并且在设备坐标系中定义尺寸信息的情况下，显示在多窗口屏幕上，显影处理性能得到改善 窗口的周边部分。 考虑到图形段的尺寸信息来扩展与窗口相关联的矩形显影区域（第一显影区域），以获得第二显影区域。 将第二开发区域与限定仅由图形段的位置信息表示的图形图像的矩形区域（存在区域）进行比较。 结果，确定图形片段是否被开发。 考虑到图形部分的尺寸信息，第一个开发区域减少，以产生第三个开发区域。 将第三开发区域与存在区域进行比较，以确定剪切操作是否对于图形段是必需的。
-
-
-
-
-
-
-
-
-
Search Results
68
records
(took 0.026 seconds)
