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    III-V semiconductor interface with graded GeSn on silicon
    1.
    发明授权
    III-V semiconductor interface with graded GeSn on silicon 有权
    III-V半导体界面，其分级GeSn在硅上

    公开(公告)号：US08889978B2

    公开(公告)日：2014-11-18

    申请号：US13619605

    申请日：2012-09-14

    Applicant: Radek Roucka ,  Michael Lebby ,  Scott Semans

    Inventor： Radek Roucka ,  Michael Lebby ,  Scott Semans

    IPC: H01L31/18

    CPC classification number: H01L31/1852 ,  H01L31/0693 ,  Y02E10/544

    Abstract: A method of depositing III-V solar collection materials on a GeSn template on a silicon substrate including the steps of providing a crystalline silicon substrate and epitaxially growing a single crystal GeSn layer on the silicon substrate using a grading profile to grade Sn through the layer. The single crystal GeSn layer has a thickness in a range of approximately 3 μm to approximately 5 μm. A layer of III-V solar collection material is epitaxially grown on the graded single crystal GeSn layer. The graded single crystal GeSn layer includes Sn up to an interface with the layer of III-V solar collection material.

    Abstract translation: 一种在硅衬底上的GeSn模板上沉积III-V太阳能收集材料的方法，包括以下步骤：使用分级轮廓提供晶体硅衬底并在硅衬底上外延生长单晶GeSn层，以通过该层对Sn进行分级。 单晶GeSn层的厚度在约3μm至约5μm的范围内。 在等级单晶GeSn层上外延生长一层III-V太阳能收集材料。 渐变的单晶GeSn层包括Sn到与III-V太阳能收集材料层的界面。

    STRAIN COMPENSATED REO BUFFER FOR III-N ON SILICON
    2.
    发明申请
    STRAIN COMPENSATED REO BUFFER FOR III-N ON SILICON 审中-公开
    用于III-N在硅中的应变补偿选择缓冲器

    公开(公告)号：US20130099357A1

    公开(公告)日：2013-04-25

    申请号：US13278952

    申请日：2011-10-21

    Applicant: Rytis Dargis ,  Erdem Arkun ,  Radek Roucka ,  Andrew Clark ,  Michael Lebby

    Inventor： Rytis Dargis ,  Erdem Arkun ,  Radek Roucka ,  Andrew Clark ,  Michael Lebby

    IPC: H01L21/20 ,  H01L29/06 ,  H01L29/20

    CPC classification number: H01L29/2003 ,  H01L21/02381 ,  H01L21/02439 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/0254 ,  H01L29/0657 ,  H01L29/16

    Abstract: A method of fabricating a rare earth oxide buffered III-N on silicon wafer including providing a crystalline silicon substrate, depositing a rare earth oxide structure on the silicon substrate including one or more layers of single crystal rare earth oxide, and depositing a layer of single crystal III-N material on the rare earth oxide structure so as to form an interface between the rare earth oxide structure and the layer of single crystal III-N material. The layer of single crystal III-N material produces a tensile stress at the interface and the rare earth oxide structure has a compressive stress at the interface dependent upon a thickness of the rare earth oxide structure. The rare earth oxide structure is grown with a thickness sufficient to provide a compressive stress offsetting at least a portion of the tensile stress at the interface to substantially reduce bowing in the wafer.

    Abstract translation: 一种在硅晶片上制造稀土氧化物缓冲III-N的方法，包括提供晶体硅衬底，在包括一层或多层单晶稀土氧化物的硅衬底上沉积稀土氧化物结构，以及沉积单层 在稀土氧化物结构上形成晶体III-N材料，以形成稀土氧化物结构和单晶III-N材料层之间的界面。 单晶III-N材料层在界面处产生拉伸应力，并且稀土氧化物结构在界面处具有取决于稀土氧化物结构的厚度的压应力。 生长稀土氧化物结构的厚度足以提供压缩应力，以抵消界面处的拉伸应力的至少一部分，从而基本上减少晶片中的弯曲。

    Low temperature epitaxial growth of quaternary wide bandgap semiconductors
    4.
    发明授权
    Low temperature epitaxial growth of quaternary wide bandgap semiconductors 失效
    四元宽带隙半导体的低温外延生长

    公开(公告)号：US06911084B2

    公开(公告)日：2005-06-28

    申请号：US09981024

    申请日：2001-10-16

    Applicant: John Kouvetakis ,  Ignatius S. T. Tsong ,  Radek Roucka ,  John Tolle

    Inventor： John Kouvetakis ,  Ignatius S. T. Tsong ,  Radek Roucka ,  John Tolle

    IPC: C30B25/02 ,  H01L21/205 ,  H01L33/26 ,  H01S5/30 ,  H01S5/32 ,  C30B25/08

    CPC classification number: H01L33/26 ,  C30B25/02 ,  C30B29/52 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/02458 ,  H01L21/02529 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02631 ,  H01S5/30 ,  H01S5/3027 ,  H01S5/32 ,  H01S2304/02

    Abstract: A method of growing quaternary epitaxial films having the formula YCZN wherein Y is a Group IV element and Z is a Group III element at temperatures in the range 550-750° C. is provided. In the method, a gaseous flux of precursor H3YCN and a vapor flux of Z atoms are introduced into a gas-source molecular beam epitaxial (GSMBE) chamber where they combine to form thin film of YCZN on the substrate. Preferred substrates are silicon, silicon carbide and AlN/silicon structures. Epitaxial thin film SiCAlN and GeCAlN are provided. Bandgap engineering may be achieved by the method by adjusting reaction parameters of the GSMBE process and the relative concentrations of the constituents of the quaternary alloy films. Semiconductor devices produced by the present method have bandgaps from about 2 eV to about 6 eV and exhibit a spectral range from visible to ultraviolet which makes them useful for a variety of optoelectronic and microelectronic applications. Large-area substrates for growth of conventional Group III nitrides and compounds are produced by SiCAlN deposited on large-diameter silicon wafers. The quaternary compounds, especially the boron containing compounds, exhibit extreme hardness. These quaternary compounds are radiation resistant and may be used in space exploration.

    Abstract translation: 提供了在550-750℃的温度下生长具有式YCZN的四元外延膜的方法，其中Y是IV族元素，Z是III族元素。 在该方法中，将前体H 3 YCN的气体流量和Z原子的蒸气通量引入气体分子束外延（GSMBE）室中，在其中它们结合形成YCZN的薄膜， 底物。 优选的衬底是硅，碳化硅和AlN /硅结构。 提供外延薄膜SiCA1N和GeCA1N。 通过调整GSMBE工艺的反应参数和四元合金薄膜成分的相对浓度，可以通过该方法实现带隙工程。 通过本方法制造的半导体器件具有约2eV至约6eV的带隙，并且具有从可见到紫外线的光谱范围，使得它们可用于各种光电子和微电子应用。 用于生长常规III族氮化物和化合物的大面积衬底由沉积在大直径硅晶片上的SiCAlN产生。 四元化合物，特别是含硼化合物，具有极高的硬度。 这些四元化合物具有耐辐射性，可用于太空探索。

    Epitaxial growth of group III nitrides on silicon substrates via a reflective lattice-matched zirconium diboride buffer layer
    6.
    发明授权
    Epitaxial growth of group III nitrides on silicon substrates via a reflective lattice-matched zirconium diboride buffer layer 有权
    通过反射晶格匹配的二硼化硼缓冲层在硅衬底上外延生长III族氮化物

    公开(公告)号：US07781356B2

    公开(公告)日：2010-08-24

    申请号：US10545484

    申请日：2004-02-12

    Applicant: John Kouvetakis ,  Ignatius S. T. Tsong ,  John Tolle ,  Radek Roucka

    Inventor： John Kouvetakis ,  Ignatius S. T. Tsong ,  John Tolle ,  Radek Roucka

    IPC: C04B35/58 ,  C30B25/00

    CPC classification number: C30B25/02 ,  C30B29/10 ,  H01L21/0237 ,  H01L21/02439 ,  H01L21/02491 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02631 ,  H01L33/007

    Abstract: A semiconductor structure and fabrication method is provided for integrating wide bandgap nitrides with silicon. The structure includes a substrate, a single crystal buffer layer formed by epitaxy over the substrate and a group III nitride film formed by epitaxy over the buffer layer. The buffer layer is reflective and conductive. The buffer layer may comprise B an element selected from the group consisting of Zr, Hf, Al. For example, the buffer layer may comprise ZrB2, AlB2 or HfB2. The buffer layer provides a lattice match with the group III nitride layer. The substrate can comprise silicon, silicon carbide (SiC), gallium arsenide (GaAs), sapphire or Al2O3. The group III nitride material includes GaN, AlN, InN, AlGaN, InGaN or AlInGaN and can form an active region. In a presently preferred embodiment, the buffer layer is ZrB2 and the substrate is Si(111) or Si(100) and the group III nitride layer comprises GaN. The ZrB2 buffer layer provides a reflective and conductive buffer layer that has a small lattice mismatch with GaN. The semiconductor structure can be used to fabricate active microelectronic devices, such as transistors including field effect transistors and bipolar transistors. The semiconductor structure also can be used to fabricate optoelectronic devices, such as laser diodes and light emitting diodes.

    Abstract translation: 提供了一种用于将宽带隙氮化物与硅结合的半导体结构和制造方法。 该结构包括衬底，通过衬底上的外延形成的单晶缓冲层和通过缓冲层上的外延形成的III族氮化物膜。 缓冲层是反射和导电的。 缓冲层可以包含选自由Zr，Hf，Al组成的组的元素。 例如，缓冲层可以包括ZrB2，AlB2或HfB2。 缓冲层提供与III族氮化物层的晶格匹配。 衬底可以包括硅，碳化硅（SiC），砷化镓（GaAs），蓝宝石或Al2O3。 III族氮化物材料包括GaN，AlN，InN，AlGaN，InGaN或AlInGaN，并且可以形成有源区。 在目前优选的实施方案中，缓冲层是ZrB 2，衬底是Si（111）或Si（100），III族氮化物层包括GaN。 ZrB2缓冲层提供与GaN具有小的晶格失配的反射和导电缓冲层。 半导体结构可用于制造有源微电子器件，例如包括场效应晶体管和双极晶体管的晶体管。 该半导体结构也可用于制造诸如激光二极管和发光二极管之类的光电器件。

    III-V SEMICONDUCTOR INTERFACE WITH GRADED GeSn ON SILICON
    8.
    发明申请
    III-V SEMICONDUCTOR INTERFACE WITH GRADED GeSn ON SILICON 有权
    III-V半导体接口与等级的GeSn在硅上

    公开(公告)号：US20140076390A1

    公开(公告)日：2014-03-20

    申请号：US13619605

    申请日：2012-09-14

    Applicant: Radek Roucka ,  Michael Lebby ,  Scott Semans

    Inventor： Radek Roucka ,  Michael Lebby ,  Scott Semans

    IPC: H01L31/065 ,  H01L31/18

    CPC classification number: H01L31/1852 ,  H01L31/0693 ,  Y02E10/544

    Abstract: A method of depositing III-V solar collection materials on a GeSn template on a silicon substrate including the steps of providing a crystalline silicon substrate and epitaxially growing a single crystal GeSn layer on the silicon substrate using a grading profile to grade Sn through the layer. The single crystal GeSn layer has a thickness in a range of approximately 3 μm to approximately 5 μm. A layer of III-V solar collection material is epitaxially grown on the graded single crystal GeSn layer. The graded single crystal GeSn layer includes Sn up to an interface with the layer of III-V solar collection material.

    Abstract translation: 一种在硅衬底上的GeSn模板上沉积III-V太阳能收集材料的方法，包括以下步骤：使用分级轮廓提供晶体硅衬底并在硅衬底上外延生长单晶GeSn层，以通过该层对Sn进行分级。 单晶GeSn层的厚度在约3μm至约5μm的范围内。 在等级单晶GeSn层上外延生长一层III-V太阳能收集材料。 渐变的单晶GeSn层包括Sn到与III-V太阳能收集材料层的界面。

    GRADED GeSn ON SILICON
    9.
    发明申请
    GRADED GeSn ON SILICON 审中-公开
    硅胶上的GeSn

    公开(公告)号：US20140053894A1

    公开(公告)日：2014-02-27

    申请号：US13593305

    申请日：2012-08-23

    Applicant: Radek Roucka ,  Michael Lebby ,  Scott Semans

    Inventor： Radek Roucka ,  Michael Lebby ,  Scott Semans

    IPC: H01L31/0336 ,  H01L31/18 ,  H01L29/267 ,  H01L21/20

    CPC classification number: H01L29/267 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02452 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/02543 ,  H01L21/02546 ,  H01L31/0687 ,  H01L31/0693 ,  H01L31/1852 ,  Y02E10/544

    Abstract: A method of fabricating a solar cell on a silicon substrate includes providing a crystalline silicon substrate, selecting a grading profile, epitaxially growing a template on the silicon substrate including a single crystal GeSn layer using the grading profile to grade Sn through the layer. The single crystal GeSn layer has a thickness in a range of approximately 3 μm to approximately 5 μm. At least two layers of high band gap material are epitaxially and sequentially grown on the template to form at least three junctions. The grading profile starts with the Sn at or near zero with the Ge at zero, the percentage of Sn varies to a maximum mid-area, and reduces the percentage of Sn to zero adjacent an upper surface.

    Abstract translation: 在硅衬底上制造太阳能电池的方法包括：提供晶体硅衬底，选择分级分布，使用分级分布在包括单晶GeSn层的硅衬底上外延生长模板，以通过该层对Sn进行分级。 单晶GeSn层的厚度在约3μm至约5μm的范围内。 外延至少两层高带隙材料，并在模板上顺序生长以形成至少三个结。 分级轮廓从Sn处于零附近开始，其中Ge处于零处，Sn的百分比变化到最大中间区域，并且将Sn的百分比减小到与上表面相邻的零。

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