公开(公告)号：US07868389B2

公开(公告)日：2011-01-11

申请号：US11928314

申请日：2007-10-30

申请人： Olubunmi O. Adetutu ,  David C. Gilmer ,  Philip J. Tobin

发明人： Olubunmi O. Adetutu ,  David C. Gilmer ,  Philip J. Tobin

IPC分类号： H01L29/76

CPC分类号： H01L21/823857 ,  H01L21/823842

摘要： One or more impurities may be incorporated within a metal-containing layer of a metal-containing gate electrode to modify the work function of the metal-containing gate electrode of a transistor can affect the threshold voltage of the transistor. In one embodiment, the impurity can be used in a p-channel transistor to allow the work function of a metal-containing gate electrode to be closer to the valence band for silicon. In another embodiment, the impurity can be used in an n-channel transistor to allow the work function of a metal-containing gate electrode to be closer to the conduction band for silicon. In a particular embodiment, a boron-containing species is implanted into a metal-containing layer within the metal-containing gate electrode within a p-channel transistor, so that the metal-containing gate electrode has a work function closer to the valence band for silicon as compared to the metal-containing gate electrode without the boron-containing species.

摘要翻译： 可以在含金属的栅电极的含金属层内并入一种或多种杂质以改变晶体管的含金属栅电极的功函数可影响晶体管的阈值电压。 在一个实施例中，杂质可用于p沟道晶体管，以允许含金属的栅电极的功函数更接近硅的价带。 在另一实施例中，杂质可用于n沟道晶体管，以允许含金属的栅电极的功函数更接近于硅的导带。 在一个具体的实施方案中，将含硼物质注入到在p沟道晶体管内的含金属栅电极内的含金属层中，使得含金属栅电极具有更接近价带的功函数 与没有含硼物质的含金属栅电极相比。

公开(公告)号：US07655550B2

公开(公告)日：2010-02-02

申请号：US11427980

申请日：2006-06-30

申请人： James K. Schaeffer ,  David C. Gilmer ,  Mark V. Raymond ,  Philip J. Tobin ,  Srikanth B. Samavedam

发明人： James K. Schaeffer ,  David C. Gilmer ,  Mark V. Raymond ,  Philip J. Tobin ,  Srikanth B. Samavedam

IPC分类号： H01L21/4763

CPC分类号： H01L27/1203 ,  H01L21/28105 ,  H01L21/823842 ,  H01L21/84 ,  H01L29/4966 ,  H01L29/517

摘要： A semiconductor device has a gate with three conductive layers over a high K gate dielectric. The first layer is substantially oxygen free. The work function is modulated to the desired work function by a second conductive layer in response to subsequent thermal processing. The second layer is a conductive oxygen-bearing metal. With sufficient thickness of the first layer, there is minimal penetration of oxygen from the second layer through the first layer to adversely impact the gate dielectric but sufficient penetration of oxygen to change the work function to a more desirable level. A third layer, which is metallic, is deposited over the second layer. A polysilicon layer is deposited over the third layer. The third layer prevents the polysilicon layer and the oxygen-bearing layer from reacting together.

摘要翻译： 半导体器件具有在高K栅极电介质上的具有三个导电层的栅极。 第一层基本上是无氧的。 响应于随后的热处理，功函数被第二导电层调制到期望的功函数。 第二层是导电含氧金属。 具有足够的第一层的厚度，氧从第二层穿过第一层的最小穿透而不利地影响栅极电介质，但充分渗入氧气以将功函数改变到更理想的水平。 金属的第三层沉积在第二层上。 多晶硅层沉积在第三层上。 第三层防止多晶硅层和含氧层一起反应。

公开(公告)号：US07432164B2

公开(公告)日：2008-10-07

申请号：US11342025

申请日：2006-01-27

申请人： Olubunmi O. Adetutu ,  David C. Gilmer ,  Philip J. Tobin

发明人： Olubunmi O. Adetutu ,  David C. Gilmer ,  Philip J. Tobin

IPC分类号： H01L21/8236 ,  H01L21/336 ,  H01L21/8234

CPC分类号： H01L21/823807 ,  H01L21/823842

摘要： A method for making a semiconductor device includes providing a first substrate region and a second substrate region, wherein at least a part of the first substrate region has a first conductivity type and at least a part of the second substrate region has a second conductivity type different from the first conductivity type. The method further includes forming a dielectric layer over at least a portion of the first substrate region and at least a portion of the second substrate region. The method further includes forming a metal-containing gate layer over at least a portion of the dielectric layer overlying the first substrate region. The method further includes introducing dopants into at least a portion of the first substrate region through the metal-containing gate layer.

摘要翻译： 一种制造半导体器件的方法包括提供第一衬底区域和第二衬底区域，其中第一衬底区域的至少一部分具有第一导电类型，并且第二衬底区域的至少一部分具有不同的第二导电类型 从第一导电类型。 该方法还包括在第一衬底区域的至少一部分和第二衬底区域的至少一部分上形成电介质层。 该方法还包括在覆盖第一衬底区域的介电层的至少一部分上形成含金属的栅极层。 该方法还包括通过含金属的栅极层将掺杂剂引入到第一衬底区域的至少一部分中。

公开(公告)号：US07297588B2

公开(公告)日：2007-11-20

申请号：US11046079

申请日：2005-01-28

申请人： Olubunmi O. Adetutu ,  David C. Gilmer ,  Philip J. Tobin

发明人： Olubunmi O. Adetutu ,  David C. Gilmer ,  Philip J. Tobin

IPC分类号： H01L21/8238

CPC分类号： H01L21/823857 ,  H01L21/823842

摘要： One or more impurities may be incorporated within a metal-containing layer of a metal-containing gate electrode to modify the work function of the metal-containing gate electrode of a transistor can affect the threshold voltage of the transistor. In one embodiment, the impurity can be used in a p-channel transistor to allow the work function of a metal-containing gate electrode to be closer to the valence band for silicon. In another embodiment, the impurity can be used in an n-channel transistor to allow the work function of a metal-containing gate electrode to be closer to the conduction band for silicon. In a particular embodiment, a boron-containing species is implanted into a metal-containing layer within the metal-containing gate electrode within a p-channel transistor, so that the metal-containing gate electrode has a work function closer to the valence band for silicon as compared to the metal-containing gate electrode without the boron-containing species.

摘要翻译： 可以在含金属的栅电极的含金属层内并入一种或多种杂质以改变晶体管的含金属栅电极的功函数可影响晶体管的阈值电压。 在一个实施例中，杂质可用于p沟道晶体管，以允许含金属的栅电极的功函数更接近硅的价带。 在另一实施例中，杂质可用于n沟道晶体管，以允许含金属的栅电极的功函数更接近于硅的导带。 在一个具体的实施方案中，将含硼物质注入到在p沟道晶体管内的含金属栅电极内的含金属层中，使得含金属栅电极具有更接近价带的功函数 与没有含硼物质的含金属栅电极相比。

公开(公告)号：US06818493B2

公开(公告)日：2004-11-16

申请号：US09916023

申请日：2001-07-26

申请人： Christopher C. Hobbs ,  Philip J. Tobin

发明人： Christopher C. Hobbs ,  Philip J. Tobin

IPC分类号： H01L218238

CPC分类号： H01L29/513 ,  H01L21/26586 ,  H01L21/28238 ,  H01L21/31122 ,  H01L29/1083 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659

摘要： A metal oxide, utilized as a gate dielectric, is removed using a combination of gaseous HCl (HCl), heat, and an absence of rf. The metal oxide, which is preferably hafnium oxide, is effectively removed in the areas not under the gate electrode. The use of HCl results in the interfacial oxide that underlies the metal oxide not being removed. The interfacial is removed to eliminate the metal and is replaced by another interfacial oxide layer. The subsequent implant steps are thus through just an interfacial oxide and not through a metal oxide. Thus, the problems associated with implanting through a metal oxide are avoided.

摘要翻译： 使用气体HCl（HCl），加热和不存在rf的组合除去用作栅极电介质的金属氧化物。 优选氧化铪的金属氧化物在不在栅极下方的区域被有效去除。 使用HCl导致不被除去的金属氧化物的界面氧化物。 除去界面以除去金属并由另一界面氧化物层代替。 因此，随后的植入步骤仅通过界面氧化物而不是通过金属氧化物。 因此，避免了通过金属氧化物注入相关的问题。

公开(公告)号：US5885870A

公开(公告)日：1999-03-23

申请号：US886927

申请日：1997-07-02

申请人： Bikas Maiti ,  Philip J. Tobin ,  Sergio A. Ajuria

发明人： Bikas Maiti ,  Philip J. Tobin ,  Sergio A. Ajuria

IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L21/336 ,  H01L27/115 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L21/28185 ,  H01L21/0214 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02332 ,  H01L21/02337 ,  H01L21/28202 ,  H01L21/3144 ,  H01L21/31662 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66825

摘要： In one embodiment a non-volatile memory device having improved reliability is formed by oxidizing a first portion of a semiconductor substrate (12) to form a first silicon dioxide layer (14). The first silicon dioxide layer (14) is then annealed and second portion of the silicon substrate, underlying the annealed silicon dioxide layer (16), is then oxidized to form a second silicon dioxide layer (18). The annealed silicon dioxide layer (16) and the second silicon dioxide layer (18) form a pre-oxide layer (20). The pre-oxide layer (20) is then nitrided to form a nitrided oxide dielectric layer (22). A floating gate is then formed overlying the nitrided oxide dielectric layer (22), which serves as the tunnel oxide for the device. Tunnel oxides formed with the inventive process are less susceptible to stress-induced leakage, and therefore, devices with improved data retention and endurance may be fabricated.

摘要翻译： 在一个实施例中，通过氧化半导体衬底（12）的第一部分以形成第一二氧化硅层（14）来形成具有改善的可靠性的非易失性存储器件。 然后退火第一二氧化硅层（14），然后氧化氧化形成第二二氧化硅层（18）的第二部分硅衬底（在退火的二氧化硅层下面）。 退火的二氧化硅层（16）和第二二氧化硅层（18）形成预氧化物层（20）。 然后将预氧化物层（20）氮化以形成氮化氧化物介电层（22）。 然后形成覆盖氮化氧化物介电层（22）的浮栅，其用作器件的隧道氧化物。 用本发明方法形成的隧道氧化物不易受到应力诱发的泄漏的影响，因此，可以制造具有改善的数据保持和耐久性的装置。

公开(公告)号：US5830802A

公开(公告)日：1998-11-03

申请号：US521720

申请日：1995-08-31

申请人： Hsing-Huang Tseng ,  Philip J. Tobin ,  Bikas Maiti

发明人： Hsing-Huang Tseng ,  Philip J. Tobin ,  Bikas Maiti

IPC分类号： H01L21/28 ,  H01L21/321 ,  H01L21/311

CPC分类号： H01L21/28061 ,  H01L21/321 ,  Y10S148/06 ,  Y10S148/147

摘要： A process for reducing halogen concentration in a material layer (56) includes the deposition of a dielectric layer (58) overlying the material layer (56). An annealing process is carried out to diffuse halogen atoms from the material layer (56) into the overlying dielectric layer (58). Once the diffusion process is complete, the dielectric layer (58) is removed.

摘要翻译： 用于降低材料层（56）中的卤素浓度的方法包括沉积覆盖在材料层（56）上的介电层（58）。 进行退火处理以将卤素原子从材料层（56）扩散到上覆电介质层（58）中。 一旦扩散过程完成，去除电介质层（58）。

公开(公告)号：US5371035A

公开(公告)日：1994-12-06

申请号：US11621

申请日：1993-02-01

申请人： James R. Pfiester ,  Philip J. Tobin

发明人： James R. Pfiester ,  Philip J. Tobin

IPC分类号： H01L21/306 ,  H01L21/32 ,  H01L21/762 ,  H01L21/302

CPC分类号： H01L21/32 ,  H01L21/30604 ,  H01L21/76202

摘要： A layer of silicon-germanium (57) allows electrical isolation structures, having reduced field oxide encroachment, to be formed without adversely effecting the adjacent active regions (64). A high etch selectivity between silicon-germanium and the silicon substrate (52) allows the silicon-germanium layer (57) to be removed, after field oxidation, without damaging the underlying active regions (64).

摘要翻译： 一层硅 - 锗（57）允许形成具有减小的场氧化物侵蚀的电隔离结构，而不会不利地影响相邻的有源区（64）。 硅 - 锗和硅衬底（52）之间的高蚀刻选择性允许在场氧化之后去除硅 - 锗层（57），而不会损坏下面的有源区域（64）。

公开(公告)号：US4914046A

公开(公告)日：1990-04-03

申请号：US305590

申请日：1989-02-03

申请人： Philip J. Tobin ,  Bich Y. Nguyen ,  Fabio Pintchovski

发明人： Philip J. Tobin ,  Bich Y. Nguyen ,  Fabio Pintchovski

IPC分类号： H01L21/28 ,  H01L21/3215 ,  H01L29/49

CPC分类号： H01L29/4925 ,  H01L21/28035 ,  H01L21/32155 ,  H01L29/4916

摘要： A polycrystalline silicon electrode and method for its fabrication are disclosed. The electrode includes a barrier layer formed by the implantation of carbon, nitrogen, or oxygen ions between two layers of polycrystalline silicon. The lower layer of polycrystalline silicon is lightly doped or undoped and the top layer is heavily doped to increase the conductivity of the electrode. The barrier layer impedes the diffusion of conductivity determining dopant impurities from one layer of polycrystalline silicon to the other.

摘要翻译： 公开了一种多晶硅电极及其制造方法。 电极包括通过在两层多晶硅之间注入碳，氮或氧离子形成的阻挡层。 多晶硅的下层被轻掺杂或未掺杂，并且顶层被重掺杂以增加电极的导电性。 阻挡层阻止导电性确定掺杂剂杂质从一层多晶硅扩散到另一层。

公开(公告)号：US4822753A

公开(公告)日：1989-04-18

申请号：US191637

申请日：1988-05-09

申请人： Faivel Pintchovski ,  Philip J. Tobin

发明人： Faivel Pintchovski ,  Philip J. Tobin

IPC分类号： H01L21/768 ,  H01L21/283 ,  H01L21/316

CPC分类号： H01L21/76879 ,  Y10S148/02 ,  Y10S148/051 ,  Y10S148/106 ,  Y10S438/926

摘要： A method is disclosed for fabricating a semiconductor device and especially for contacting a semiconductor device. A silicon substrate is provided which has a device region formed at the surface thereof and which is contacted with a silicide. An insulating layer overlies the substrate and has an opening therethrough which exposes a portion of that device region. Titanium nitride is deposited in a blanket layer overlying the silicide and the insulating layer. A leveling agent such as a spin-on glass is applied to the structure to substantially fill the opening. That leveling agent is then anisotropically etched to leave the leveling agent only in the opening. The leveling agent is used as an etch mask to remove the portion of titanium nitride which is located outside the opening. After removing the remaining leveling agent, the titanium nitride in the opening is used as a nucleating surface for the selective deposition of a tungsten plug which fills the contact opening. The titanium nitride layer serves as both a nucleating surface and as a barrier layer which separates the tungsten from the underlying silicon.

摘要翻译： 公开了用于制造半导体器件的方法，特别是用于接触半导体器件。 提供硅衬底，其具有在其表面形成并与硅化物接触的器件区域。 绝缘层覆盖在衬底上并具有通过其穿过的开口，露出该器件区域的一部分。 氮化钛沉积在覆盖硅化物和绝缘层的覆盖层中。 将均化剂如旋涂玻璃施加到结构上以基本上填充开口。 然后对流平剂进行各向异性蚀刻，仅在开口处离开流平剂。 流平剂用作蚀刻掩模以去除位于开口外部的氮化钛部分。 在除去剩余的流平剂之后，将开口中的氮化钛用作用于选择性沉积填充接触开口的钨丝塞的成核表面。 氮化钛层既用作成核的表面又用作将钨与下面的硅分离开的阻挡层。