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    SYSTEM AND METHOD FOR DEBUGGING SCAN CHAINS
    1.
    发明申请
    SYSTEM AND METHOD FOR DEBUGGING SCAN CHAINS 有权
    用于调查扫描链的系统和方法

    公开(公告)号：US20120246531A1

    公开(公告)日：2012-09-27

    申请号：US13071512

    申请日：2011-03-25

    Applicant: Sandeep Jain ,  Nikila Krishnamoorthy ,  Abhishek Chaudhary ,  Nipun Mahajan ,  Saurabh Chauhan

    Inventor： Sandeep Jain ,  Nikila Krishnamoorthy ,  Abhishek Chaudhary ,  Nipun Mahajan ,  Saurabh Chauhan

    IPC: G01R31/28 ,  G06F11/00

    CPC classification number: G01R31/318547 ,  G01R31/318558

    Abstract: Scan chains are used to detect faults in integrated circuits but with the size of today's circuits, it is difficult to detect and locate scan chain faults, especially when the scan data in and scan data out have been compressed. A method for debugging scan chains includes selecting a scan chain for debugging using a scan chain selection block and then providing scan test vectors to the selected scan chain. The scan test vectors undergo various scan test stages to generate scan response vectors. The scan response vectors are compared with ideal response vectors to identify a failing scan chain.

    Abstract translation: 扫描链用于检测集成电路中的故障，但随着当今电路的大小，难以检测和定位扫描链故障，特别是当扫描数据输入和扫描数据输出被压缩时。 用于调试扫描链的方法包括使用扫描链选择块选择用于调试的扫描链，然后向所选择的扫描链提供扫描测试向量。 扫描测试矢量经历各种扫描测试阶段以产生扫描响应矢量。 将扫描响应向量与理想响应向量进行比较，以识别故障扫描链。

    Testing of modules operating with different characteristics of control signals using scan based techniques
    2.
    发明申请
    Testing of modules operating with different characteristics of control signals using scan based techniques 有权
    使用基于扫描的技术测试使用不同控制信号特性的模块

    公开(公告)号：US20050091562A1

    公开(公告)日：2005-04-28

    申请号：US10710451

    申请日：2004-07-12

    Applicant: Nikila KRISHNAMOORTHY ,  Anindya SAHA ,  Rubin PAREKHJI

    Inventor： Nikila KRISHNAMOORTHY ,  Anindya SAHA ,  Rubin PAREKHJI

    IPC: G01R31/3185 ,  G01R31/28

    CPC classification number: G01R31/318563

    Abstract: Testing of modules (such as Intellectual property (IP) cores) in integrated circuits (such as system on a chip units (SOCs)) in situations when different modules operate with different characteristics of a control signal. In an embodiment, another module (“subsystem module”) may be implemented to be tested with any of a multiple characteristics of a control signal, and a register which is programmable to generate a derived control signal of a desired characteristic from an original control signal, is provided. The derived control signal is provided to test the subsystem module. According to an aspect of the invention the desired characteristic may be determined, for example, to test a path between the two modules at the same speed as at which the path would be operated in a functional mode.

    Abstract translation: 在不同模块以不同控制信号的特性运行的情况下，集成电路（例如芯片单元（SOC）中的系统）中的模块（例如知识产权（IP）核心）的测试。 在一个实施例中，另一个模块（“子系统模块”）可以被实现为用控制信号的多个特性中的任何一个进行测试，以及寄存器，其被编程以从原始控制信号产生所需特性的导出控制信号 ，被提供。 提供导出的控制信号以测试子系统模块。 根据本发明的一个方面，可以确定期望的特性，例如，以与功能模式下操作路径相同的速度来测试两个模块之间的路径。

    At-speed ATPG testing and apparatus for SoC designs having multiple clock domain using a VLCT test platform
    3.
    发明授权
    At-speed ATPG testing and apparatus for SoC designs having multiple clock domain using a VLCT test platform 有权
    使用VLCT测试平台的高速ATPG测试和SoC设计的设备具有多个时钟域

    公开(公告)号：US07134061B2

    公开(公告)日：2006-11-07

    申请号：US10731714

    申请日：2003-12-09

    Applicant: Anupama Aniruddha Agashe ,  Nikila Krishnamoorthy ,  Anindya Saha ,  Rubin A. Parekhji

    Inventor： Anupama Aniruddha Agashe ,  Nikila Krishnamoorthy ,  Anindya Saha ,  Rubin A. Parekhji

    IPC: G01R31/28

    CPC classification number: G01R31/318552

    Abstract: A scan test circuitry design imbedded on an SoC having the scan architecture of a VLCT platform is disclosed herein. This BIST circuitry design that is not limited in the number of scan test ports supported includes at least one scan chain group having a corresponding clock domain that couples to receive test stimulus data. Each scan chain group has a corresponding test mode signal to shift the test stimulus data at a shift clock rate derived from its corresponding clock domain. A controlling demultiplexer connects to each multiplexer unit within each scan chain group to provide control signals for shifting in the test stimulus. A clock control mechanism provides a control signal for each scan chain to shift test stimulus and capture resultant data. Furthermore, when a simultaneous test mode signal is enabled, the clock control mechanism couples to each scan chain to enable simultaneous capture of each scan chain group.

    Abstract translation: 本文公开了嵌入在具有VLCT平台的扫描架构的SoC上的扫描测试电路设计。 该BIST电路设计不受所支持的扫描测试端口数量的限制，包括至少一个具有耦合以接收测试激励数据的相应时钟域的扫描链组。 每个扫描链组具有对应的测试模式信号，以从其对应的时钟域导出的移位时钟速率移动测试激励数据。 控制解复用器连接到每个扫描链组内的每个多路复用器单元，以提供用于在测试刺激中移位的控制信号。 时钟控制机制为每个扫描链提供控制信号，以移动测试刺激并捕获结果数据。 此外，当启用同时测试模式信号时，时钟控制机制耦合到每个扫描链以实现每个扫描链组的同时捕获。

    Mixed-signal core design for concurrent testing of mixed-signal, analog, and digital components
    6.
    发明申请
    Mixed-signal core design for concurrent testing of mixed-signal, analog, and digital components 有权
    混合信号核心设计，用于混合信号，模拟和数字组件的并发测试

    公开(公告)号：US20050065747A1

    公开(公告)日：2005-03-24

    申请号：US10677150

    申请日：2003-10-01

    Applicant: Amit Premy ,  Vudutha Suresh Gupta ,  Anupama Agashe ,  Nikila Krishnamoorthy ,  Rubin Parekhji

    Inventor： Amit Premy ,  Vudutha Suresh Gupta ,  Anupama Agashe ,  Nikila Krishnamoorthy ,  Rubin Parekhji

    IPC: G01R27/28 ,  G01R31/00 ,  G01R31/14 ,  G01R31/3167 ,  G01R31/317 ,  G01R31/3185 ,  G06F19/00 ,  G06J1/00

    CPC classification number: G06J1/00 ,  G01R31/3167 ,  G01R31/31704 ,  G01R31/3172 ,  G01R31/318533

    Abstract: A mixed-signal core disclosed herein is designed for efficient concurrent testing analog, mixed-signal, and digital components. One tester may test all components and, thereby, reduce test time without losing full test coverage. An analog module includes all the analog and mixed-signal components of the mixed-signal core, while a first digital module includes digital components required for functional/parametric verification of the mixed-signal components within the analog module. A first virtual boundary connects the analog and the first digital modules to gate the signal transfer during testing. A second digital module includes the remaining digital components of the mixed-signal core, whereby a second virtual boundary separates it from the first digital module. This type of partitioning enables the mixed-signal core to have three modes of operation, wherein the first mode of operation provides digital interface characterization testing of the first and second digital module and analog characterization/trimming testing of the analog module. In the second mode of operation, concurrent testing of the analog module and the first and second digital module is conducted; wherein analog characterization/trimming testing is performed on the analog module and digital interface characterization testing is performed on the first digital module, while SCAN/BIST testing is performed on the second digital module. In the third mode of operation, non-concurrent testing of the analog module, the first digital module, and the second digital module is enabled; wherein SCAN/BIST testing of the first digital module and the second digital module is enabled, while the analog module is powered down.

    Abstract translation: 本文公开的混合信号芯片被设计用于有效并发测试模拟，混合信号和数字组件。 一个测试人员可以测试所有组件，从而减少测试时间，而不会损失完整的测试覆盖范围。 模拟模块包括混合信号核心的所有模拟和混合信号组件，而第一数字模块包括模拟量模块内混合信号组件的功能/参数验证所需的数字组件。 第一个虚拟边界将模拟和第一个数字模块连接起来，以在测试期间对信号传输进行门控。 第二数字模块包括混合信号核心的剩余数字分量，由此第二虚拟边界将其与第一数字模块分离。 这种分区使得混合信号核心具有三种操作模式，其中第一操作模式提供第一和第二数字模块的数字接口表征测试以及模拟模块的模拟表征/修整测试。 在第二种操作模式下，对模拟模块和第一和第二数字模块进行并行测试; 其中对模拟模块执行模拟表征/修整测试，并且在第一数字模块上执行数字接口表征测试，同时在第二数字模块上执行扫描/ BIST测试。 在第三种操作模式下，模拟模块，第一个数字模块和第二个数字模块的非并发测试被启用; 其中模拟模块被断电时，启用第一数字模块和第二数字模块的扫描/ BIST测试。

    System and method for debugging scan chains
    7.
    发明授权
    System and method for debugging scan chains 有权
    用于调试扫描链的系统和方法

    公开(公告)号：US08458541B2

    公开(公告)日：2013-06-04

    申请号：US13071512

    申请日：2011-03-25

    Applicant: Sandeep Jain ,  Nikila Krishnamoorthy ,  Abhishek Chaudhary ,  Nipun Mahajan ,  Saurabh Chauhan

    Inventor： Sandeep Jain ,  Nikila Krishnamoorthy ,  Abhishek Chaudhary ,  Nipun Mahajan ,  Saurabh Chauhan

    IPC: G01R31/28

    CPC classification number: G01R31/318547 ,  G01R31/318558

    Abstract: Scan chains are used to detect faults in integrated circuits but with the size of today's circuits, it is difficult to detect and locate scan chain faults, especially when the scan data in and scan data out have been compressed. A method for debugging scan chains includes selecting a scan chain for debugging using a scan chain selection block and then providing scan test vectors to the selected scan chain. The scan test vectors undergo various scan test stages to generate scan response vectors. The scan response vectors are compared with ideal response vectors to identify a failing scan chain.

    Abstract translation: 扫描链用于检测集成电路中的故障，但随着当今电路的大小，难以检测和定位扫描链故障，特别是当扫描数据输入和扫描数据输出被压缩时。 用于调试扫描链的方法包括使用扫描链选择块选择用于调试的扫描链，然后向所选择的扫描链提供扫描测试向量。 扫描测试矢量经历各种扫描测试阶段以产生扫描响应矢量。 将扫描响应向量与理想响应向量进行比较，以识别故障扫描链。

    Testing of modules operating with different characteristics of control signals using scan based techniques
    9.
    发明授权
    Testing of modules operating with different characteristics of control signals using scan based techniques 有权
    使用基于扫描的技术测试使用不同控制信号特性的模块

    公开(公告)号：US07213184B2

    公开(公告)日：2007-05-01

    申请号：US10710451

    申请日：2004-07-12

    Applicant: Nikila Krishnamoorthy ,  Anindya Saha ,  Rubin Ajit Parekhji

    Inventor： Nikila Krishnamoorthy ,  Anindya Saha ,  Rubin Ajit Parekhji

    IPC: G01R31/28 ,  H03K19/096

    CPC classification number: G01R31/318563

    Abstract: Testing of modules (such as Intellectual property (IP) cores) in integrated circuits (such as system on a chip units (SOCs)) in situations when different modules operate with different characteristics of a control signal. In an embodiment, another module (“subsystem module”) may be implemented to be tested with any of a multiple characteristics of a control signal, and a register which is programmable to generate a derived control signal of a desired characteristic from an original control signal, is provided. The derived control signal is provided to test the subsystem module. According to an aspect of the invention the desired characteristic may be determined, for example, to test a path between the two modules at the same speed as at which the path would be operated in a functional mode.

    Abstract translation: 在不同模块以不同控制信号的特性运行的情况下，集成电路（例如芯片单元（SOC）中的系统）中的模块（例如知识产权（IP）核心）的测试。 在一个实施例中，另一个模块（“子系统模块”）可以被实现为用控制信号的多个特性中的任何一个进行测试，以及寄存器，其被编程以从原始控制信号产生所需特性的导出控制信号 ，被提供。 提供导出的控制信号以测试子系统模块。 根据本发明的一个方面，可以确定期望的特性，例如，以与功能模式下操作路径相同的速度来测试两个模块之间的路径。

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