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    STRUCTURES AND CONTROL PROCESSES FOR EFFICIENT GENERATION OF DIFFERENT TEST CLOCKING SEQUENCES, CONTROLS AND OTHER TEST SIGNALS IN SCAN DESIGNS WITH MULTIPLE PARTITIONS, AND DEVICES, SYSTEMS AND PROCESSES OF MAKING
    1.
    发明申请
    STRUCTURES AND CONTROL PROCESSES FOR EFFICIENT GENERATION OF DIFFERENT TEST CLOCKING SEQUENCES, CONTROLS AND OTHER TEST SIGNALS IN SCAN DESIGNS WITH MULTIPLE PARTITIONS, AND DEVICES, SYSTEMS AND PROCESSES OF MAKING 有权
    用于有效生成具有多个分区的扫描设计中的不同测试时序，控制和其他测试信号的结构和控制过程，以及设备，系统和制造过程

    公开(公告)号：US20120030532A1

    公开(公告)日：2012-02-02

    申请号：US12938939

    申请日：2010-11-03

    Applicant: Arvind Jain ,  Prashant Mohan Kulkarni ,  Srinivas Kumar Vooka ,  Sundarrajan Subramanian ,  Rubin Ajit Parekhji

    Inventor： Arvind Jain ,  Prashant Mohan Kulkarni ,  Srinivas Kumar Vooka ,  Sundarrajan Subramanian ,  Rubin Ajit Parekhji

    IPC: G01R31/28 ,  G06F11/16

    CPC classification number: G01R31/318547

    Abstract: A scannable integrated circuit (100) including a functional integrated circuit (P1, P2) having scan chains, multiple scan decompressors (120.1, 120.2), each operable to supply scan bits to some of the scan chains (101.k, 102.k), a shared scan-programmable control circuit (110, 300), a tree circuit (400) coupled with the functional integrated circuit (P1, P2), the shared scan-programmable control circuit (110, 300) coupled to control the tree circuit (400), and a selective coupling circuit (180) operable to provide selective coupling with the shared scan-programmable control circuit (110, 300) for scan programming through any of the multiple scan decompressors (120.1, 120.2). Other circuits, devices, systems, and processes of operation and manufacture are disclosed.

    Abstract translation: 一种可扫描集成电路（100），包括具有扫描链的功能集成电路（P1，P2），多个扫描解压缩器（120.1,120.2），每个扫描解压缩器可操作以将扫描比特提供给扫描链中的某些扫描链（101.k， 共享扫描可编程控制电路（110,300），与所述功能集成电路（P1，P2）耦合的树电路（400），所述共享扫描可编程控制电路（110,300）被耦合以控制所述树 电路（400）和选择耦合电路（180），其可操作以提供与共享扫描可编程控制电路（110,300）的选择性耦合，用于通过任何多个扫描解压缩器（120.1,120.2）进行扫描编程。 公开了其他电路，设备，系统以及操作和制造过程。

    Integrated circuits capable of generating test mode control signals for scan tests
    2.
    发明授权
    Integrated circuits capable of generating test mode control signals for scan tests 有权
    能够产生用于扫描测试的测试模式控制信号的集成电路

    公开(公告)号：US08972807B2

    公开(公告)日：2015-03-03

    申请号：US13470863

    申请日：2012-05-14

    Applicant: Rajesh Mittal ,  Puneet Sabbarwal ,  Prakash Narayanan ,  Rubin Ajit Parekhji

    Inventor： Rajesh Mittal ,  Puneet Sabbarwal ,  Prakash Narayanan ,  Rubin Ajit Parekhji

    IPC: G01R31/28 ,  G01R31/3185 ,  G01R31/3183 ,  G01R31/3177

    CPC classification number: G01R31/318555 ,  G01R31/3177 ,  G01R31/3183 ,  G01R31/318533 ,  G01R31/318536 ,  G01R31/318544 ,  G01R31/318569 ,  G01R31/318594

    Abstract: Various embodiments of methods and integrated circuits capable of generating a test mode control signal for a scan test through a scan chain (such as in an integrated circuit) are provided. The integrated circuit includes a test pattern detection block, a counter circuit, and a control circuit. The test pattern detection block is configured to receive a detection pattern and to detect a first pattern corresponding to a shift phase and a second pattern corresponding to a capture phase of a test pattern based on the detection pattern and to generate a trigger signal based upon the detection of the patterns. The control circuit generates and controls the test mode control signal based on the count states. The counter circuit is configured to generate one or more count states corresponding to one of the shift phase, the capture phase and the clock signal based on the detected pattern.

    Abstract translation: 提供了能够通过扫描链（例如集成电路）产生用于扫描测试的测试模式控制信号的方法和集成电路的各种实施例。 集成电路包括测试图案检测块，计数器电路和控制电路。 测试图案检测块被配置为接收检测图案并且基于检测图案检测对应于移位相位和对应于测试图案的捕获相位的第二图案的第一图案，并且基于该检测图案生成触发信号 检测图案。 控制电路根据计数状态生成并控制测试模式控制信号。 计数器电路被配置为基于检测到的图案产生与移位相位，捕获相位和时钟信号之一相对应的一个或多个计数状态。

    Interruptible non-destructive run-time built-in self-test for field testing
    3.
    发明授权
    Interruptible non-destructive run-time built-in self-test for field testing 有权
    中断非破坏性运行时内置自检进行现场测试

    公开(公告)号：US08799713B2

    公开(公告)日：2014-08-05

    申请号：US13407474

    申请日：2012-02-28

    Applicant: Swathi Gangasani ,  Srinivasulu Alampally ,  Prohor Chowdhury ,  Srinivasa B S Chakravarthy ,  Padmini Sampath ,  Rubin Ajit Parekhji

    Inventor： Swathi Gangasani ,  Srinivasulu Alampally ,  Prohor Chowdhury ,  Srinivasa B S Chakravarthy ,  Padmini Sampath ,  Rubin Ajit Parekhji

    IPC: G06F11/00 ,  G06F11/27

    CPC classification number: G06F11/27

    Abstract: A built-in self-test (BIST) diagnostic system tests the execution of a processor. The processor is arranged to execute a normal application for controlling a process that is external to the processor. The normal execution is executed in normal execution timeslots that have idle timeslots that are interspersed in time between the normal execution timeslots. A BIST controller is arranged to detect the presence of an idle timeslot in the execution of the processor and to use a scan chain to scan-in a first test pattern for a test application for testing the processor. The first test pattern is executed by the processor during the detected idle timeslot and a first result pattern generated by the execution of the first test pattern is scanned-out. The scanned-out first test pattern is evaluated to determine the presence of an error. The first test pattern application is conditionally interruptible.

    Abstract translation: 内置的自检（BIST）诊断系统可以测试处理器的执行情况。 处理器被布置为执行用于控制处理器外部的进程的正常应用程序。 正常执行在具有在正常执行时隙之间的时间上散布的空闲时隙的正常执行时隙中执行。 BIST控制器被布置成在执行处理器时检测空闲时隙的存在，并且使用扫描链来扫描用于测试处理器的测试应用的第一测试模式。 在检测到的空闲时隙期间由处理器执行第一测试模式，并且扫描由执行第一测试模式产生的第一结果模式。 对扫描出的第一测试图案进行评估以确定是否存在错误。 第一个测试模式应用程序是有条件的中断。

    INTERRUPTIBLE NON-DESTRUCTIVE RUN-TIME BUILT-IN SELF-TEST FOR FIELD TESTING
    4.
    发明申请
    INTERRUPTIBLE NON-DESTRUCTIVE RUN-TIME BUILT-IN SELF-TEST FOR FIELD TESTING 有权
    用于现场测试的中断非破坏性运行时建立自检

    公开(公告)号：US20120226942A1

    公开(公告)日：2012-09-06

    申请号：US13407474

    申请日：2012-02-28

    Applicant: Swathi Gangasani ,  Srinivasulu Alampally ,  Prohor Chowdhury ,  Srinivasa B S Chakravarthy ,  Padmini Sampath ,  Rubin Ajit Parekhji

    Inventor： Swathi Gangasani ,  Srinivasulu Alampally ,  Prohor Chowdhury ,  Srinivasa B S Chakravarthy ,  Padmini Sampath ,  Rubin Ajit Parekhji

    IPC: G06F11/27

    CPC classification number: G06F11/27

    Abstract: A built-in self-test (BIST) diagnostic system tests the execution of a processor. The processor is arranged to execute a normal application for controlling a process that is external to the processor. The normal execution is executed in normal execution timeslots that have idle timeslots that are interspersed in time between the normal execution timeslots. A BIST controller is arranged to detect the presence of an idle timeslot in the execution of the processor and to use a scan chain to scan-in a first test pattern for a test application for testing the processor. The first test pattern is executed by the processor during the detected idle timeslot and a first result pattern generated by the execution of the first test pattern is scanned-out. The scanned-out first test pattern is evaluated to determine the presence of an error. The first test pattern application is conditionally interruptible.

    Abstract translation: 内置的自检（BIST）诊断系统可以测试处理器的执行情况。 处理器被布置为执行用于控制处理器外部的进程的正常应用程序。 正常执行在具有在正常执行时隙之间的时间上散布的空闲时隙的正常执行时隙中执行。 BIST控制器被布置成在执行处理器时检测空闲时隙的存在，并且使用扫描链来扫描用于测试处理器的测试应用的第一测试模式。 在检测到的空闲时隙期间由处理器执行第一测试模式，并且扫描由执行第一测试模式产生的第一结果模式。 对扫描出的第一测试图案进行评估以确定是否存在错误。 第一个测试模式应用程序是有条件的中断。

    Testing of modules operating with different characteristics of control signals using scan based techniques
    5.
    发明授权
    Testing of modules operating with different characteristics of control signals using scan based techniques 有权
    使用基于扫描的技术测试使用不同控制信号特性的模块

    公开(公告)号：US07213184B2

    公开(公告)日：2007-05-01

    申请号：US10710451

    申请日：2004-07-12

    Applicant: Nikila Krishnamoorthy ,  Anindya Saha ,  Rubin Ajit Parekhji

    Inventor： Nikila Krishnamoorthy ,  Anindya Saha ,  Rubin Ajit Parekhji

    IPC: G01R31/28 ,  H03K19/096

    CPC classification number: G01R31/318563

    Abstract: Testing of modules (such as Intellectual property (IP) cores) in integrated circuits (such as system on a chip units (SOCs)) in situations when different modules operate with different characteristics of a control signal. In an embodiment, another module (“subsystem module”) may be implemented to be tested with any of a multiple characteristics of a control signal, and a register which is programmable to generate a derived control signal of a desired characteristic from an original control signal, is provided. The derived control signal is provided to test the subsystem module. According to an aspect of the invention the desired characteristic may be determined, for example, to test a path between the two modules at the same speed as at which the path would be operated in a functional mode.

    Abstract translation: 在不同模块以不同控制信号的特性运行的情况下，集成电路（例如芯片单元（SOC）中的系统）中的模块（例如知识产权（IP）核心）的测试。 在一个实施例中，另一个模块（“子系统模块”）可以被实现为用控制信号的多个特性中的任何一个进行测试，以及寄存器，其被编程以从原始控制信号产生所需特性的导出控制信号 ，被提供。 提供导出的控制信号以测试子系统模块。 根据本发明的一个方面，可以确定期望的特性，例如，以与功能模式下操作路径相同的速度来测试两个模块之间的路径。

    Scan compression architecture with bypassable scan chains for low test mode power
    7.
    发明授权
    Scan compression architecture with bypassable scan chains for low test mode power 有权
    扫描压缩架构，具有旁路扫描链，可实现低测试模式电源

    公开(公告)号：US08856601B2

    公开(公告)日：2014-10-07

    申请号：US12868253

    申请日：2010-08-25

    Applicant: Srivaths Ravi ,  Rajesh Kumar Tiwari ,  Rubin Ajit Parekhji

    Inventor： Srivaths Ravi ,  Rajesh Kumar Tiwari ,  Rubin Ajit Parekhji

    IPC: G01R31/28 ,  G01R31/3185 ,  G01R31/3177

    CPC classification number: G01R31/3177 ,  G01R31/318547

    Abstract: This invention permits selectively bypasses serial scan chains. Constant or low toggle data is directed to the bypassed serial scan chain, thus reducing power consumption. The number and identity of serial scan chains bypassed during a particular test can be changed dynamically dependent upon the semiconductor process variations of a particular integrated circuit. This enables an optimal test to be preformed for integrated circuits having differing semiconductor process variations.

    Abstract translation: 本发明允许有选择地绕过串行扫描链。 恒定或低电平触发数据被引导到旁路的串行扫描链，从而降低功耗。 在特定测试期间旁路的串行扫描链的数量和身份可以根据特定集成电路的半导体工艺变化动态地改变。 这使得能够对具有不同半导体工艺变化的集成电路进行最佳测试。

    Scan Compression Architecture with Bypassable Scan Chains for Low Test Mode Power
    8.
    发明申请
    Scan Compression Architecture with Bypassable Scan Chains for Low Test Mode Power 有权
    扫描压缩架构与低测试模式电源的可选扫描链

    公开(公告)号：US20130159800A1

    公开(公告)日：2013-06-20

    申请号：US12868253

    申请日：2010-08-25

    Applicant: Srivaths Ravi ,  Rajesh Kumar Tiwari ,  Rubin Ajit Parekhji

    Inventor： Srivaths Ravi ,  Rajesh Kumar Tiwari ,  Rubin Ajit Parekhji

    IPC: G01R31/3177

    CPC classification number: G01R31/3177 ,  G01R31/318547

    Abstract: This invention permits selectively bypasses serial scan chains. Constant or low toggle data is directed to the bypassed serial scan chain, thus reducing power consumption. The number and identity of serial scan chains bypassed during a particular test can be changed dynamically dependent upon the semiconductor process variations of a particular integrated circuit. This enables an optimal test to be preformed for integrated circuits having differing semiconductor process variations.

    Abstract translation: 本发明允许有选择地绕过串行扫描链。 恒定或低电平触发数据被引导到旁路的串行扫描链，从而降低功耗。 在特定测试期间旁路的串行扫描链的数量和身份可以根据特定集成电路的半导体工艺变化而动态地改变。 这使得能够对具有不同半导体工艺变化的集成电路进行最佳测试。

    ENHANCED CONTROL IN SCAN TESTS OF INTEGRATED CIRCUITS WITH PARTITIONED SCAN CHAINS
    9.
    发明申请
    ENHANCED CONTROL IN SCAN TESTS OF INTEGRATED CIRCUITS WITH PARTITIONED SCAN CHAINS 有权
    集成电路扫描测试与分区扫描链的增强控制

    公开(公告)号：US20110099442A1

    公开(公告)日：2011-04-28

    申请号：US12604397

    申请日：2009-10-23

    Applicant: Alan David Hales ,  Srujan Kumar Nakidi ,  Rubin Ajit Parekhji ,  Srivaths Ravi ,  Rajesh Kumar Tiwari

    Inventor： Alan David Hales ,  Srujan Kumar Nakidi ,  Rubin Ajit Parekhji ,  Srivaths Ravi ,  Rajesh Kumar Tiwari

    IPC: G01R31/3177 ,  G06F11/25

    CPC classification number: G01R31/318533

    Abstract: A test controller implemented in an integrated circuit (IC) with partitioned scan chains provides enhanced control in performing scan tests. According to an aspect, a test controller can selectively control scan-in, scan-out and capture phases of scan tests for different scan chains of the IC to be independent. The number of pins required to interface the test controller with an external tester is less than the number of partitions that the test controller can support. According to another aspect, an IC includes a register corresponding to each partition to support transition fault (or LOS) testing. According to another aspect, an IC with partitioned scan chains includes serial to parallel and parallel to serial converters, thereby minimizing the external pins required to support scan tests.

    Abstract translation: 在具有划分的扫描链的集成电路（IC）中实现的测试控制器在执行扫描测试时提供增强的控制。 根据一个方面，测试控制器可以选择性地控制对于IC的不同扫描链的扫描测试的扫描扫描和捕获阶段是独立的。 将测试控制器与外部测试仪连接所需的引脚数小于测试控制器可以支持的分区数。 根据另一方面，IC包括对应于每个分区的寄存器以支持转换故障（或LOS）测试。 根据另一方面，具有划分扫描链的IC包括串行到并行并行串行转换器，从而最小化支持扫描测试所需的外部引脚。

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