公开(公告)号：US20050065747A1

公开(公告)日：2005-03-24

申请号：US10677150

申请日：2003-10-01

Applicant: Amit Premy ,  Vudutha Suresh Gupta ,  Anupama Agashe ,  Nikila Krishnamoorthy ,  Rubin Parekhji

Inventor： Amit Premy ,  Vudutha Suresh Gupta ,  Anupama Agashe ,  Nikila Krishnamoorthy ,  Rubin Parekhji

IPC: G01R27/28 ,  G01R31/00 ,  G01R31/14 ,  G01R31/3167 ,  G01R31/317 ,  G01R31/3185 ,  G06F19/00 ,  G06J1/00

CPC classification number: G06J1/00 ,  G01R31/3167 ,  G01R31/31704 ,  G01R31/3172 ,  G01R31/318533

Abstract: A mixed-signal core disclosed herein is designed for efficient concurrent testing analog, mixed-signal, and digital components. One tester may test all components and, thereby, reduce test time without losing full test coverage. An analog module includes all the analog and mixed-signal components of the mixed-signal core, while a first digital module includes digital components required for functional/parametric verification of the mixed-signal components within the analog module. A first virtual boundary connects the analog and the first digital modules to gate the signal transfer during testing. A second digital module includes the remaining digital components of the mixed-signal core, whereby a second virtual boundary separates it from the first digital module. This type of partitioning enables the mixed-signal core to have three modes of operation, wherein the first mode of operation provides digital interface characterization testing of the first and second digital module and analog characterization/trimming testing of the analog module. In the second mode of operation, concurrent testing of the analog module and the first and second digital module is conducted; wherein analog characterization/trimming testing is performed on the analog module and digital interface characterization testing is performed on the first digital module, while SCAN/BIST testing is performed on the second digital module. In the third mode of operation, non-concurrent testing of the analog module, the first digital module, and the second digital module is enabled; wherein SCAN/BIST testing of the first digital module and the second digital module is enabled, while the analog module is powered down.

Abstract translation: 本文公开的混合信号芯片被设计用于有效并发测试模拟，混合信号和数字组件。 一个测试人员可以测试所有组件，从而减少测试时间，而不会损失完整的测试覆盖范围。 模拟模块包括混合信号核心的所有模拟和混合信号组件，而第一数字模块包括模拟量模块内混合信号组件的功能/参数验证所需的数字组件。 第一个虚拟边界将模拟和第一个数字模块连接起来，以在测试期间对信号传输进行门控。 第二数字模块包括混合信号核心的剩余数字分量，由此第二虚拟边界将其与第一数字模块分离。 这种分区使得混合信号核心具有三种操作模式，其中第一操作模式提供第一和第二数字模块的数字接口表征测试以及模拟模块的模拟表征/修整测试。 在第二种操作模式下，对模拟模块和第一和第二数字模块进行并行测试; 其中对模拟模块执行模拟表征/修整测试，并且在第一数字模块上执行数字接口表征测试，同时在第二数字模块上执行扫描/ BIST测试。 在第三种操作模式下，模拟模块，第一个数字模块和第二个数字模块的非并发测试被启用; 其中模拟模块被断电时，启用第一数字模块和第二数字模块的扫描/ BIST测试。