公开(公告)号：US06981190B2

公开(公告)日：2005-12-27

申请号：US10259288

申请日：2002-09-30

Applicant: Ajit D. Gupte ,  Jais Abraham

Inventor： Ajit D. Gupte ,  Jais Abraham

IPC: G11C29/10 ,  G11C29/48 ,  G01R31/28

CPC classification number: G11C29/10 ,  G11C29/48 ,  G11C2029/3202

Abstract: A launch multiplexor which enables a desired bit to be stored into a desired memory element when using sequential scanning techniques (e.g., automatic test pattern generation (ATPG)). The launch multiplexor may be employed in addition to a scan multiplexor, which enables the test pattern bits or normal operating input to be selected and stored in the desired memory element. The scan multiplexor is used to scan-in a test pattern and evaluate a first input, and the launch multiplexor provides the control to store a desired bit into the corresponding memory element. Another output may be evaluated after storing the desired bit. In an embodiment, launch multiplexors are used associated with only memory elements in the critical paths, and the delay in transitioning from one output to another may be conveniently measured.

Abstract translation: 一种使用顺序扫描技术（例如，自动测试模式生成（ATPG）））使发射多路复用器能够将期望的位存储到期望的存储元件中。 除了扫描多路复用器之外，可以采用发射多路复用器，这使得能够选择并存储在期望的存储器元件中的测试图案位或正常操作输入。 扫描多路复用器用于扫描测试模式并评估第一输入，并且启动多路复用器提供将所需位存储到相应的存储器元件中的控制。 存储所需位后可以评估另一个输出。 在一个实施例中，启动多路复用器仅与关键路径中的存储器元件相关联，并且可以方便地测量从一个输出到另一个输出的转换延迟。

公开(公告)号：US20080001616A1

公开(公告)日：2008-01-03

申请号：US11308931

申请日：2006-05-26

Applicant: Jais ABRAHAM ,  Rohit GOEL

Inventor： Jais ABRAHAM ,  Rohit GOEL

IPC: G01R31/26

CPC classification number: G01R31/318572 ,  G01R31/31858

Abstract: Testing the components of I/O paths in an integrated circuit at at-speed operation (i.e., the speed at which the integrated circuit would be operated during normal non-test mode). In an embodiment, boundary scan cells of different paths are connected in a scan chain, and each scan cell tests the corresponding component (e.g., buffer) by launching data at a first time instance and receiving the result of the data at a second time instance, with the duration between the first time instance and the second time instance corresponding to the at-speed operation. If the data is received accurately, the component may be deemed to be operating accurately at-speed.

Abstract translation: 以高速运行（即，在正常非测试模式下集成电路将运行的速度）测试集成电路中的I / O路径的组件。 在一个实施例中，不同路径的边界扫描单元被连接在扫描链中，并且每个扫描单元通过在第一时间实例发射数据并在第二时间实例接收数据的结果来测试对应的组件（例如，缓冲器） 具有对应于全速操作的第一时间实例和第二时间间隔之间的持续时间。 如果准确地接收到数据，则该部件可能被认为是以高速精确的操作。

公开(公告)号：US20060248422A1

公开(公告)日：2006-11-02

申请号：US11160235

申请日：2005-06-15

Applicant: Naga Satya Puvvada ,  Nikila Krishnamoorthy ,  Sandeep Jain ,  Jais Abraham

Inventor： Naga Satya Puvvada ,  Nikila Krishnamoorthy ,  Sandeep Jain ,  Jais Abraham

IPC: G01R31/28

CPC classification number: G01R31/318594

Abstract: According to an aspect of present invention, modules designed to operate with different frequency in functional (normal) mode are tested using a sequential scan based technique at the respective frequencies. In one embodiment the interface logic connecting the two modules is tested for at-speed performance (i.e., the same speed at which the interface would be operated in functional mode during normal operation).

Abstract translation: 根据本发明的一个方面，使用基于顺序扫描的技术在各个频率上测试被设计为在功能（正常）模式下以不同频率工作的模块。 在一个实施例中，连接两个模块的接口逻辑被测试为高速性能（即，在正常操作期间接口将在功能模式下操作的相同速度）。

公开(公告)号：US07082558B2

公开(公告)日：2006-07-25

申请号：US10302886

申请日：2002-11-25

Applicant: Ajit D. Gupte ,  Shankaranarayana Karantha Deshamangala ,  Amit Brahme ,  Jais Abraham

Inventor： Ajit D. Gupte ,  Shankaranarayana Karantha Deshamangala ,  Amit Brahme ,  Jais Abraham

IPC: G11C29/00

CPC classification number: G11C29/025 ,  G01R31/318328 ,  G11C29/02 ,  G11C29/10 ,  G11C29/50012

Abstract: A non-robust test pattern, which causes a transition on a path of interest as well as off-paths, may be selected as being suitable for performing delay analysis of the path of interest (e.g., critical path) if the transitions caused on the off-paths would not overlap with the transition caused on the path of interest. In other words, an aspect of the present invention enables at least some non-robust test patterns to be used for performing delay analysis. As non-robust test patterns (as well as robust test patterns) can be used to perform delay analysis, the number of possible test patterns for performing speed analysis can be increased.

Abstract translation: 可以选择导致感兴趣的路径和离开路径上的转换的非鲁棒性测试模式，以适合于对所关注的路径（例如，关键路径）进行延迟分析，如果在 偏离路径不会与感兴趣的路径上引起的过渡重叠。 换句话说，本发明的一个方面使得能够使用至少一些非鲁棒性测试模式来执行延迟分析。 由于非鲁棒性测试模式（以及鲁棒的测试模式）可用于执行延迟分析，因此可以增加用于执行速度分析的可能测试模式的数量。

公开(公告)号：US07421634B2

公开(公告)日：2008-09-02

申请号：US11160235

申请日：2005-06-15

Applicant: Naga Satya Srikanth Puvvada ,  Nikila Krishnamoorthy ,  Sandeep Jain ,  Jais Abraham

Inventor： Naga Satya Srikanth Puvvada ,  Nikila Krishnamoorthy ,  Sandeep Jain ,  Jais Abraham

IPC: G01R31/28

CPC classification number: G01R31/318594

Abstract: According to an aspect of present invention, modules designed to operate with different frequency in functional (normal) mode are tested using a sequential scan based technique at the respective frequencies. In one embodiment the interface logic connecting the two modules is tested for at-speed performance (i.e., the same speed at which the interface would be operated in functional mode during normal operation).

Abstract translation: 根据本发明的一个方面，使用基于顺序扫描的技术在各个频率上测试被设计为在功能（正常）模式下以不同频率工作的模块。 在一个实施例中，连接两个模块的接口逻辑被测试为高速性能（即，在正常操作期间接口将在功能模式下操作的相同速度）。

公开(公告)号：US07404126B2

公开(公告)日：2008-07-22

申请号：US11308481

申请日：2006-03-29

Applicant: Sandeep Jain ,  Jais Abraham

Inventor： Sandeep Jain ,  Jais Abraham

IPC: G01R31/28

CPC classification number: G01R31/318544 ,  G01R31/318547 ,  G01R31/318566

Abstract: Scan tests tolerant to indeterminate states generated in an integrated circuit (IC) when employing signature analysis to analyze test outputs. Bits with indeterminate-state are masked when scanning out the bits from the scan chains to force such indeterminate bits to a known logic level. This prevents a signature generator receiving the outputs of a scan test from generating an invalid signature. In an embodiment, masking information is stored in encoded form in a memory. A decoding circuit decodes the masking information and provides mask data under control from a mask controller. Mask data is sent to a masking circuit which also receives corresponding bits from scan-out vectors, with each scan-out vector being generated by a corresponding one of multiple scan chains. The output of the masking circuit may be provided in a compressed form to the signature generator circuit.

Abstract translation: 当采用签名分析来分析测试输出时，扫描测试可以容忍在集成电路（IC）中产生的不确定状态。 当扫描扫描链中的位以将这种不确定位强制到已知逻辑电平时，具有不确定状态的位被屏蔽。 这防止签名生成器接收到扫描测试的输出而生成无效签名。 在一个实施例中，屏蔽信息以编码形式存储在存储器中。 解码电路对掩蔽信息进行解码，并在掩模控制器的控制下提供掩模数据。 掩模数据被发送到屏蔽电路，屏蔽电路也从扫描向量接收对应的位，每个扫描向量由多个扫描链中相应的一个生成。 掩蔽电路的输出可以以压缩形式提供给签名生成器电路。

公开(公告)号：US07352169B2

公开(公告)日：2008-04-01

申请号：US11308931

申请日：2006-05-26

Applicant: Jais Abraham ,  Rohit Goel

Inventor： Jais Abraham ,  Rohit Goel

IPC: G01R31/26

CPC classification number: G01R31/318572 ,  G01R31/31858

Abstract: Testing the components of I/O paths in an integrated circuit at-speed operation (i.e., the speed at which the integrated circuit would be operated during normal non-test mode). In an embodiment, boundary scan cells of different paths are connected in a scan chain, and each scan cell tests the corresponding component (e.g., buffer) by launching data at a first time instance and receiving the result of the data at a second time instance, with the duration between the first time instance and the second time instance corresponding to the at-speed operation. If the data is received accurately, the component may be deemed to be operating accurately at-speed.

Abstract translation: 在集成电路中以速度运行（即，在正常非测试模式下集成电路将运行的速度）测试I / O路径的组件。 在一个实施例中，不同路径的边界扫描单元被连接在扫描链中，并且每个扫描单元通过在第一时间实例发射数据并在第二时间实例接收数据的结果来测试对应的组件（例如，缓冲器） 具有对应于全速操作的第一时间实例和第二时间间隔之间的持续时间。 如果准确地接收到数据，则该部件可能被认为是以高速精确的操作。

公开(公告)号：US20070234150A1

公开(公告)日：2007-10-04

申请号：US11308481

申请日：2006-03-29

Applicant: Sandeep Jain ,  Jais Abraham

Inventor： Sandeep Jain ,  Jais Abraham

IPC: G01R31/28

CPC classification number: G01R31/318544 ,  G01R31/318547 ,  G01R31/318566

Abstract: Scan tests tolerant to indeterminate states generated in an integrated circuit (IC) when employing signature analysis to analyze test outputs. Bits with indeterminate-state are masked when scanning out the bits from the scan chains to force such indeterminate bits to a known logic level. This prevents a signature generator receiving the outputs of a scan test from generating an invalid signature. In an embodiment, masking information is stored in encoded form in a memory. A decoding circuit decodes the masking information and provides mask data under control from a mask controller. Mask data is sent to a masking circuit which also receives corresponding bits from scan-out vectors, with each scan-out vector being generated by a corresponding one of multiple scan chains. The output of the masking circuit may be provided in a compressed form to the signature generator circuit.

Abstract translation: 当采用签名分析来分析测试输出时，扫描测试可以容忍在集成电路（IC）中产生的不确定状态。 当扫描扫描链中的位以将这种不确定位强制到已知逻辑电平时，具有不确定状态的位被屏蔽。 这防止签名生成器接收到扫描测试的输出而生成无效签名。 在一个实施例中，屏蔽信息以编码形式存储在存储器中。 解码电路对掩蔽信息进行解码，并在掩模控制器的控制下提供掩模数据。 掩模数据被发送到屏蔽电路，屏蔽电路也从扫描向量接收对应的位，每个扫描向量由多个扫描链中相应的一个生成。 掩蔽电路的输出可以以压缩形式提供给签名生成器电路。

公开(公告)号：US06853212B2

公开(公告)日：2005-02-08

申请号：US10324900

申请日：2002-12-20

Applicant: G. Subash Chandar ,  Jais Abraham

Inventor： G. Subash Chandar ,  Jais Abraham

IPC: H03K3/012 ,  H03K3/037 ,  H03K3/3562 ,  H03K19/00

CPC classification number: H03K3/012 ,  H03K3/0375 ,  H03K3/35625

Abstract: A scannable storage circuit is provided that has a separate a scan output buffer for driving the scan output. The scan output buffer is coupled to the storage element in a parallel manner with the data output buffer so that normal data propagation is not delayed. The scan output buffer is gated by a scan enable input so that the scan output is quiescent when the storage circuit is not in scan mode. The selectively enabled scan output buffer is embodied with only four transistors.

Abstract translation: 提供了一种可扫描存储电路，其具有用于驱动扫描输出的单独的扫描输出缓冲器。 扫描输出缓冲器以与数据输出缓冲器并行的方式耦合到存储元件，使得正常的数据传播不被延迟。 扫描输出缓冲器由扫描使能输入选通，使得当存储电路不处于扫描模式时，扫描输出静止。 选择使能的扫描输出缓冲器仅具有四个晶体管。