公开(公告)号：US08105078B2

公开(公告)日：2012-01-31

申请号：US11702591

申请日：2007-02-06

申请人： Naoshi Adachi

发明人： Naoshi Adachi

IPC分类号： C23C16/04

CPC分类号： F27D5/0037 ,  C04B2235/9623 ,  H01L21/67306 ,  H01L21/67309

摘要： A heat treatment jig for semiconductor silicon substrates is configured such that a cristobalitized oxide film is formed in a region where the cristobalitized oxide film is in contact with a silicon substrate backside. When said heat treatment jig is used, generation of a slip can be prevented during heat treatment. In the case where the heat treatment jig is used in combination with a shielding plate, particles are further prevented from adhering to the silicon substrate surface to maintain quality characteristics of the semiconductor silicon substrate at a higher level, and device production yield can largely be improved. The heat treatment jig can easily be manufactured by introducing a cristobalitization promoting agent to a surface or in the vicinity of a surface of the heat treatment jig, performing the heat treatment at temperatures in the range of 1000 to 1380° C., and repeating the introduction of the cristobalitization promoting agent and the heat treatment.

摘要翻译： 用于半导体硅衬底的热处理夹具被构造成使得在刻蚀的氧化膜与硅衬底背面接触的区域中形成刻板化的氧化物膜。 当使用所述热处理夹具时，可以在热处理期间防止产生滑动。 在将热处理夹具与屏蔽板组合使用的情况下，进一步防止了粒子附着在硅衬底表面上，从而将半导体硅衬底的质量特性保持在更高的水平，并且能够大幅提高器件的制造成品率 。 热处理夹具可以容易地通过向热处理夹具的表面或表面附近引入澄清促进剂，在1000〜1380℃的温度范围内进行热处理，并重复 引入明显促进剂和热处理。

公开(公告)号：US07331780B2

公开(公告)日：2008-02-19

申请号：US11239096

申请日：2005-09-30

申请人： Naoshi Adachi

发明人： Naoshi Adachi

IPC分类号： F27D5/00

CPC分类号： H01L21/67306 ,  H01L21/67103 ,  H01L21/67309 ,  H01L21/68735 ,  H01L21/6875 ,  H01L21/68757

摘要： A heat treatment jig by the invention comprising: the diameter of a disk-type structure being 60% or more of that of loaded semiconductor wafers; the thickness being 1.0 mm or more but 10 mm or less; the surface roughness Ra of 0.1 μm or more but 100 μm or less at a contacting surface with the wafers; and the surface planarity being specifically controlled in the concentric direction as well as in the diametrical direction, otherwise in place of above planarity, comprising a controlled maximum height in such a way that the maximum height is obtained by the flatness measurement at the multiple positions and the difference between said maximum height and the hypothetical-average-height-plane thus set is 50 μm or less, can reduce the slip generation due to the close adhesion of the wafers and the jig. Owing to this, even if the wafers having large tare weight should be heat-treated, the slip generation can be effectively prevented, thus enabling the jig to be widely used as the reliable heat treatment jig for semiconductor substrates.

摘要翻译： 本发明的热处理夹具包括：盘型结构的直径为装载的半导体晶片的直径的60％以上; 厚度为1.0mm以上且10mm以下; 与晶片的接触面的表面粗糙度Ra为0.1μm以上且100μm以下; 并且表面平面度被特别地在同心方向以及直径方向上被控制，否则代替上述平面度，包括受控的最大高度，使得最大高度通过在多个位置处的平坦度测量获得，并且 所述最大高度与所设定的假想平均高度面之间的差为50um或更小，可以减少由于晶片和夹具紧密附着而产生的滑移。 因此，即使对具有大皮重的晶片进行热处理，也可以有效地防止滑移产生，从而能够将夹具广泛用作半导体基板的可靠的热处理夹具。

公开(公告)号：US20060078839A1

公开(公告)日：2006-04-13

申请号：US11239096

申请日：2005-09-30

申请人： Naoshi Adachi

发明人： Naoshi Adachi

IPC分类号： F27D5/00

CPC分类号： H01L21/67306 ,  H01L21/67103 ,  H01L21/67309 ,  H01L21/68735 ,  H01L21/6875 ,  H01L21/68757

摘要： A heat treatment jig by the invention comprising: the diameter of a disk-type structure being 60% or more of that of loaded semiconductor wafers; the thickness being 1.0 mm or more but 10 mm or less; the surface roughness Ra of 0.1 μm or more but 100 μm or less at a contacting surface with the wafers; and the surface planarity being specifically controlled in the concentric direction as well as in the diametrical direction, otherwise in place of above planarity, comprising a controlled maximum height in such a way that the maximum height is obtained by the flatness measurement at the multiple positions and the difference between said maximum height and the hypothetical-average-height-plane thus set is 50 μm or less, can reduce the slip generation due to the close adhesion of the wafers and the jig. Owing to this, even if the wafers having large tare weight should be heat-treated, the slip generation can be effectively prevented, thus enabling the jig to be widely used as the reliable heat treatment jig for semiconductor substrates.

摘要翻译： 本发明的热处理夹具包括：盘型结构的直径为装载的半导体晶片的直径的60％以上; 厚度为1.0mm以上且10mm以下; 与晶片的接触面的表面粗糙度Ra为0.1μm以上且100μm以下; 并且表面平面度被特别地在同心方向以及直径方向上被控制，否则代替上述平面度，包括受控的最大高度，使得最大高度通过在多个位置处的平坦度测量获得，并且 所述最大高度与所设定的假想平均高度面之间的差为50um或更小，可以减少由于晶片和夹具紧密附着而产生的滑移。 因此，即使对具有大皮重的晶片进行热处理，也可以有效地防止滑移产生，从而能够将夹具广泛用作半导体基板的可靠的热处理夹具。

公开(公告)号：US20050282101A1

公开(公告)日：2005-12-22

申请号：US11039968

申请日：2005-01-24

申请人： Naoshi Adachi

发明人： Naoshi Adachi

IPC分类号： F27D5/00 ,  H01L21/22 ,  H01L21/31 ,  H01L21/324 ,  H01L21/673 ,  H01L21/68

CPC分类号： H01L21/67306 ,  F27D5/0037 ,  H01L21/67303 ,  H01L21/67309 ,  H01L21/6732 ,  H01L21/67323

摘要： A heat treatment jig for supporting silicon semiconductor substrates by contacting, being loaded onto a heat treatment boat in a vertical heat treatment furnace, comprises; the configuration of a ring or a disc structure with the wall thickness between 1.5 and 6.0 mm; the deflection displacement of 100 μm or less at contact region in loaded condition; the outer diameter which is 65% or more of the diameter of said substrate; and the surface roughness (Ra) of between 1.0 and 100 μm at the contact region. The use of said jig enables to effectively retard the slip generation and to avoid the growth hindrance of thermally oxidized film at the back surface of said substrate, diminishing the surface steps causing the defocus in photolithography step in device fabrication process, thereby enabling to maintain high quality of silicon semiconductor substrates and to substantially enhance the device yield.

摘要翻译： 一种用于通过在立式热处理炉中加载到热处理船上的接触来支撑硅半导体衬底的热处理夹具包括： 环形或圆盘结构的结构，壁厚在1.5至6.0毫米之间; 载荷条件下接触区偏转位移为100mum以下; 外径为所述基材的直径的65％以上。 和接触区域的表面粗糙度（Ra）在1.0和100μm之间。 使用所述夹具能够有效地延缓滑移产生并避免热氧化膜在所述基板的背面的增长阻碍，减少在器件制造过程中在光刻步骤中导致散焦的表面步骤，由此能够保持高 硅半导体衬底的质量并且显着提高器件产量。

公开(公告)号：US6129787A

公开(公告)日：2000-10-10

申请号：US212389

申请日：1998-12-16

申请人： Naoshi Adachi ,  Masakazu Sano ,  Shinsuke Sadamitsu ,  Tsuyoshi Kubota

发明人： Naoshi Adachi ,  Masakazu Sano ,  Shinsuke Sadamitsu ,  Tsuyoshi Kubota

IPC分类号： H01L21/31 ,  C30B33/02 ,  H01L21/02 ,  H01L21/316 ,  H01L21/322 ,  H01L21/324 ,  C30B25/02

CPC分类号： H01L21/3225

摘要： An object of the present invention is to provide a single-crystal silicon wafer where octahedral voids of Grown-in defects, which are the generation source of COP on the surface and COP at several .mu.m depth of the surface layer of the single-crystal silicon wafer grown by the CZ method, are effectively eliminated, and a fabrication method of this wafer, where oxygen near the surface is out-diffused by annealing in a hydrogen and/or inactive gas ambient and oxide film on the inner walls of the octahedral voids near the surface are removed by the created unsaturated oxygen area, then oxidation annealing is performed in an oxygen ambient or mixed gas ambient of oxygen and inactive gas, so that interstitial silicon atoms are forcibly injected to completely eliminate the octahedral voids near the surface, and at the same time an IG layer is created in the bulk of the wafer.

摘要翻译： 本发明的目的是提供一种单晶硅晶片，其中，作为表面上的COP的生成源的生长缺陷的八面体空隙和单晶表面层的几μm深度的COP 通过CZ方法生长的硅晶片被有效地消除，并且该晶片的制造方法，其中表面附近的氧气在氢气和/或非活性气体环境中退火并在八面体内壁上的氧化膜扩散 通过产生的不饱和氧区域去除表面附近的空隙，然后在氧环境或氧气和惰性气体的混合气体环境中进行氧化退火，使得强制注入间隙硅原子以完全消除表面附近的八面体空隙， 并且同时在晶片的大部分中产生IG层。

公开(公告)号：US6074479A

公开(公告)日：2000-06-13

申请号：US327383

申请日：1999-06-08

申请人： Naoshi Adachi ,  Takehiro Hisatomi ,  Masakazu Sano

发明人： Naoshi Adachi ,  Takehiro Hisatomi ,  Masakazu Sano

IPC分类号： H01L21/322 ,  H01L21/324 ,  H01L21/673 ,  F27D5/00 ,  B05C13/00 ,  C30B35/00

CPC分类号： H01L21/67303 ,  H01L21/3225 ,  H01L21/324 ,  H01L21/67309 ,  Y10S206/832 ,  Y10S206/833 ,  Y10T117/1016

摘要： This invention anneals a vertical stack of two or more groups of unseparated wafers, with approximately 10 wafers in each group. The invention makes it possible to anneal more wafers in a single annealing operation under a variety of conditions, including: oxygen outer diffusion annealing to form a denuded zone; annealing to control bulk micro defects and provide intrinsic gettering functions; annealing to enhance gate oxide integrity by eliminating crystal-originated particles from the wafer surface and internal grown-in or as-grown defects; and suppression of dislocation and slip in elevated temperature environments.

摘要翻译： 本发明退回了两组或更多组未分离晶片的垂直堆叠，每组中约有10个晶片。 本发明使得可以在各种条件下的单个退火操作中退火更多的晶片，包括：氧外扩散退火以形成剥离区; 退火以控制大量微缺陷并提供固有的吸气功能; 退火以通过从晶片表面去除晶体起始的颗粒和内部生长或成长的缺陷来提高栅极氧化物的完整性; 并在高温环境中抑制位错和滑移。

公开(公告)号：US5508207A

公开(公告)日：1996-04-16

申请号：US199170

申请日：1994-04-26

申请人： Masataka Horai ,  Naoshi Adachi ,  Hideshi Nishikawa ,  Masakazu Sano

发明人： Masataka Horai ,  Naoshi Adachi ,  Hideshi Nishikawa ,  Masakazu Sano

IPC分类号： H01L21/02 ,  H01L21/205 ,  H01L21/30 ,  H01L21/322 ,  H01L21/324 ,  H01L21/306

CPC分类号： H01L21/3003 ,  H01L21/3221 ,  Y10S117/906 ,  Y10S148/003 ,  Y10S148/022 ,  Y10S148/024 ,  Y10S438/909

摘要： The present invention provides a method of manufacturing a semiconductor wafer whereby (1) deterioration of a micro-roughness in a low temperature range in hydrogen atmospheric treatment and increase of resistivity due to outward diffusion of an electrically active impurity in a high temperature range are prevented; (2) in the heat treatment in a hydrogen gas atmosphere, the concentration of gas molecules in the atmosphere, such as water, oxygen and the like, are brought to 5 ppm or less in water molecule conversion; and a reaction is suppressed in which a substrate surface is oxidized unequally and the micro-roughness deteriorates; and (3) the same kind of impurity as the electrically active impurity contained in a Si substrate is mixed into the atmosphere and the outward diffusion of the impurity in the vicinity of the Si substrate surface is prevented to prevent variation of the resistivity.

摘要翻译： PCT No.PCT / JP93 / 00865 Sec。 371日期1994年04月26日 102（e）日期1994年4月26日PCT提交1993年6月25日PCT公布。 出版物WO94 / 00872 日本1994年1月6日。本发明提供一种制造半导体晶片的方法，其中（1）在大气氢处理中的低温范围内的微粗糙度的劣化以及由于电活性杂质的向外扩散引起的电阻率的增加 在高温范围内被防止; （2）在氢气气氛中的热处理中，水分子等氧化物等气氛中的气体分子的浓度在水分子转化率为5ppm以下。 并且抑制基板表面不均匀氧化并且微粗糙度劣化的反应; 和（3）将与Si衬底中含有的电活性杂质相同的杂质混入大气中，并且防止杂质在Si衬底表面附近的向外扩散以防止电阻率的变化。

公开(公告)号：US08568537B2

公开(公告)日：2013-10-29

申请号：US13215031

申请日：2011-08-22

申请人： Naoshi Adachi ,  Tamio Motoyama

发明人： Naoshi Adachi ,  Tamio Motoyama

IPC分类号： H01L21/322 ,  H01L21/02 ,  C30B25/02 ,  C30B25/18 ,  C30B29/06

CPC分类号： H01L21/3221 ,  C30B25/02 ,  C30B25/18 ,  C30B29/06 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02532

摘要： An epitaxial wafer comprises a silicon substrate, a gettering epitaxial film formed thereon and containing silicon and carbon, and a main silicon epitaxial film formed on the gettering epitaxial film, in which the gettering epitaxial film has a given carbon atom concentration and carbon atoms are existent between its silicon lattices.

摘要翻译： 外延晶片包括硅基板，形成在其上并含有硅和碳的吸杂外延膜，以及形成在吸杂外延膜上的主硅外延膜，其中吸杂外延膜具有给定的碳原子浓度和碳原子存在 在它的硅晶格之间。

公开(公告)号：US07442038B2

公开(公告)日：2008-10-28

申请号：US11463993

申请日：2006-08-11

申请人： Naoshi Adachi

发明人： Naoshi Adachi

IPC分类号： F27D5/00

CPC分类号： H01L21/6875 ,  F27D5/0037 ,  H01L21/67748

摘要： This invention provides a heat treatment jig for semiconductor silicon substrates, which, in respective heat treatment of hydrogen annealing or argon annealing, can handle enlargement of the diameter of wafers to be treated and can also prevent slipping and dislocations that occur as a result of the stress caused by the weight of the wafer itself or the deflection of the heat treatment jig itself.

摘要翻译： 本发明提供了一种用于半导体硅基板的热处理夹具，其在氢退火或氩退火的各自热处理中可以处理待处理的晶片的直径的扩大，并且还可以防止由于所述待处理而导致的滑动和位错 由晶片本身的重量或热处理夹具本身的挠曲引起的应力。

公开(公告)号：US20080090384A1

公开(公告)日：2008-04-17

申请号：US11632875

申请日：2005-07-19

申请人： Naoshi Adachi ,  Yukio Komatsu

发明人： Naoshi Adachi ,  Yukio Komatsu

IPC分类号： H01L21/322

CPC分类号： H01L21/76243 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02299 ,  H01L21/26533 ,  H01L21/31662

摘要： A manufacturing method for a SIMOX substrate for obtaining a SIMOX substrate by subjecting a silicon substrate having oxygen ions implanted thereinto by heat treatment at 1300 to 1350° C. in an atmosphere of a gas mixture of argon and oxygen, the method includes: performing a pre-heat-treatment to the silicon substrate for five minutes to four hours within the temperature range of 1000° C. to 1280° C. in an atmosphere of inert gas, reducing gas, or a gas mixture of inert gas and reducing gas, after the oxygen ions are implanted and before the heat treatment is performed.

摘要翻译： 一种SIMOX基板的制造方法，其特征在于，在氩气和氧气的气体混合气体中，通过在1300〜1350℃下进行热处理，对其中含有氧离子的硅基板进行了处理，从而获得SIMOX基板，该方法包括： 在惰性气体，还原气体或惰性气体与还原气体的气体混合气体中，在1000℃〜1280℃的温度范围内，对硅基板进行预热处理5分钟〜4小时， 在氧离子植入之后并且在进行热处理之前。