公开(公告)号：US20050132814A1

公开(公告)日：2005-06-23

申请号：US11049872

申请日：2005-02-04

Applicant: Shinya Satou ,  Satoshi Shimada ,  Atsuo Watanabe ,  Yasuo Onose ,  Seiji Kuryu ,  Atsushi Miyazaki ,  Junichi Horie ,  Naohiro Momma

Inventor： Shinya Satou ,  Satoshi Shimada ,  Atsuo Watanabe ,  Yasuo Onose ,  Seiji Kuryu ,  Atsushi Miyazaki ,  Junichi Horie ,  Naohiro Momma

IPC: B81B3/00 ,  B81B7/00 ,  G01L7/08 ,  G01L9/00 ,  H01L21/00

CPC classification number: B81C1/00333 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81C1/00293 ,  B81C2203/0145 ,  G01L9/0042 ,  G01L9/0073

Abstract: The object of the present invention is to propose an etch channel sealing structure characterized by excellent impermeability to moisture and resistance to temporal change of the diaphragm in the pressure sensor produced according to the sacrificial layer etching technique, and to provide a pressure sensor characterized by excellent productivity and durability. After a very small gap is formed by the sacrificial layer etching technique, silicon oxide film is deposited by the CVD technique or the like, there by sealing the etch channel. Further, impermeable thin film of polysilicon or the like is formed to cover the oxide film. This allows an etch channel sealing structure to be simplified in the pressure sensor produced according to the sacrificial layer etching technique, and prevents entry of moisture into the cavity, thereby improving moisture resistance. Moreover, sealing material with small film stress reduces temporal deformation of the diaphragm.

Abstract translation: 本发明的目的是提出一种蚀刻通道密封结构，其特征在于对根据牺牲层蚀刻技术制造的压力传感器中的防潮性和抗隔膜的时间变化具有优异的防渗性，并且提供了一种特征在于优异的压力传感器 生产力和耐久性。 在通过牺牲层蚀刻技术形成非常小的间隙之后，通过密封蚀刻通道，通过CVD技术等沉积氧化硅膜。 此外，形成多晶硅等的不渗透性薄膜以覆盖氧化物膜。 这允许在根据牺牲层蚀刻技术产生的压力传感器中简化蚀刻通道密封结构，并且防止水分进入空腔，从而改善耐湿性。 此外，具有小膜应力的密封材料减小了隔膜的时间变形。

公开(公告)号：USRE34158E

公开(公告)日：1993-01-12

申请号：US744514

申请日：1991-08-13

Applicant: Atsuo Watanabe ,  Takahiro Nagano ,  Takahide Ikeda ,  Naohiro Momma ,  Ryuichi Saito

Inventor： Atsuo Watanabe ,  Takahiro Nagano ,  Takahide Ikeda ,  Naohiro Momma ,  Ryuichi Saito

IPC: H01L21/762 ,  H01L21/763 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092

CPC classification number: H01L27/0928 ,  H01L21/76224 ,  H01L21/763 ,  H01L21/823892 ,  H01L27/0623

Abstract: A monolithic complementary semiconductor device comprising n-type and p-type well regions separated by a dielectric isolation region extending from the surface into the substrate region. The well region includes a highly doped buried region which is located at the bottom of the well region and separates an active region in the wall from the substrate region. The isolation region is deeper than the buried region. The well-to-well isolation is enhanced by the combination of the buried region and the deep dielectric isolation region. Packing density and the high speed operation can also be improved.

公开(公告)号：US4879041A

公开(公告)日：1989-11-07

申请号：US172583

申请日：1988-03-24

Applicant: Hideaki Kurokawa ,  Akira Yamada ,  Yasuo Koseki ,  Harumi Matsuzaki ,  Katsuya Ebara ,  Sankichi Takahashi ,  Hiroaki Yoda ,  Nobuatsu Hayashi ,  Isao Okouchi ,  Yukio Hishinuma ,  Naohiro Momma

Inventor： Hideaki Kurokawa ,  Akira Yamada ,  Yasuo Koseki ,  Harumi Matsuzaki ,  Katsuya Ebara ,  Sankichi Takahashi ,  Hiroaki Yoda ,  Nobuatsu Hayashi ,  Isao Okouchi ,  Yukio Hishinuma ,  Naohiro Momma

IPC: B01D3/06 ,  C02F1/04

CPC classification number: B01D61/364 ,  B01D3/06 ,  C02F1/045 ,  Y10S210/90

Abstract: The present invention relates to a process for producing ultra-pure water, an apparatus for producing said ultra-pure water and a process for using the ultra-pure water produced according to said process. More particularly, the present invention relates to a process for producing ultra-pure water which comprises boiling a raw water to vaporize off the volatile components from the raw water, subsequently generating steam from the water, contacting the steam with a hydrophobic, porous, gas-permeable and liquid-impermeable membrane to make the steam permeate the membrane, and then condensing the steam, as well as to an apparatus for producing said ultra-pure water and a process for using said ultra-pure water.

公开(公告)号：US4862240A

公开(公告)日：1989-08-29

申请号：US85260

申请日：1987-08-12

Applicant: Atsuo Watanabe ,  Takahiro Nagano ,  Takahide Ikeda ,  Naohiro Momma ,  Ryuichi Saito

Inventor： Atsuo Watanabe ,  Takahiro Nagano ,  Takahide Ikeda ,  Naohiro Momma ,  Ryuichi Saito

IPC: H01L29/78 ,  H01L21/74 ,  H01L21/762 ,  H01L21/763 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092

CPC classification number: H01L21/76224 ,  H01L21/74 ,  H01L21/76205 ,  H01L21/763 ,  H01L21/823892 ,  H01L27/092 ,  H01L27/0623

Abstract: A monolithic complementary semiconductor device comprising n-type and p-type well regions separated by a dielectric isolation region extending from the surface into the substrate region. The well region includes a highly doped buried region which is located at the bottom of the well region and separates an active region in the well from the substrate region. The isolation region is deeper than the buried region. The well-to-well isolation is enhanced by the combination of the buried region and the deep dielectric isolation region. Packing density and the high speed operation can also be improved.

Abstract translation: 一种单片互补半导体器件，包括由从表面延伸到衬底区域的电介质隔离区隔开的n型和p型阱区。 阱区域包括高度掺杂的掩埋区域，其位于阱区域的底部并且将阱中的有源区域与衬底区域分离。 隔离区域比掩埋区域深。 通过掩埋区域和深介电隔离区域的组合增强了井对阱隔离。 包装密度和高速运转也可以提高。

公开(公告)号：US06892582B1

公开(公告)日：2005-05-17

申请号：US09936480

申请日：1999-08-20

Applicant: Shinya Satou ,  Satoshi Shimada ,  Atsuo Watanabe ,  Yasuo Onose ,  Seiji Kuryu ,  Atsushi Miyazaki ,  Junichi Horie ,  Naohiro Momma

Inventor： Shinya Satou ,  Satoshi Shimada ,  Atsuo Watanabe ,  Yasuo Onose ,  Seiji Kuryu ,  Atsushi Miyazaki ,  Junichi Horie ,  Naohiro Momma

IPC: B81B3/00 ,  B81B7/00 ,  G01L7/08 ,  G01L9/00 ,  H01L21/00

CPC classification number: B81C1/00333 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81C1/00293 ,  B81C2203/0145 ,  G01L9/0042 ,  G01L9/0073

Abstract: The object of the present invention is to propose an etch channel sealing structure characterized by excellent impermeability to moisture and resistance to temporal change of the diaphragm in the pressure sensor produced according to the sacrificial layer etching technique, and to provide a pressure sensor characterized by excellent productivity and durability. After a very small gap is formed by the sacrificial layer etching technique, silicon oxide film is deposited by the CVD technique or the like, thereby sealing the etch channel. Further, impermeable thin film of polysilicon or the like is formed to cover the oxide film.This allows an etch channel sealing structure to be simplified in the pressure sensor produced according to the sacrificial layer etching technique, and prevents entry of moisture into the cavity, thereby improving moisture resistance. Moreover, sealing material with small film stress reduces temporal deformation of the diaphragm.

Abstract translation: 本发明的目的是提出一种蚀刻通道密封结构，其特征在于对根据牺牲层蚀刻技术制造的压力传感器中的防潮性和抗隔膜的时间变化具有优异的防渗性，并且提供一种特征在于优异的压力传感器 生产力和耐久性。 在通过牺牲层蚀刻技术形成非常小的间隙之后，通过CVD技术等沉积氧化硅膜，从而密封蚀刻通道。 此外，形成多晶硅等的不渗透性薄膜以覆盖氧化物膜。 这允许在根据牺牲层蚀刻技术产生的压力传感器中简化蚀刻通道密封结构，并且防止水分进入空腔，从而改善耐湿性。 此外，具有小膜应力的密封材料减小了隔膜的时间变形。

公开(公告)号：US06621701B2

公开(公告)日：2003-09-16

申请号：US10195561

申请日：2002-07-16

Applicant: Akihiro Tamba ,  Takayoshi Nakamura ,  Ryuichi Saito ,  Naohiro Momma

Inventor： Akihiro Tamba ,  Takayoshi Nakamura ,  Ryuichi Saito ,  Naohiro Momma

IPC: H05H720

CPC classification number: H05K7/20927 ,  H01L2924/0002 ,  H01L2924/1627 ,  H01L2924/00

Abstract: According to the invention, there is provided a water cooled inverter structure forming a plurality of shallow cavities and deep cavities in a housing, fixing a bottom surface of power semiconductor modules to shallow cavities to form a shallow water channel and directly cooling the power semiconductor modules using this shallow water channel. Since cooling water flows fast in the shallow water channel, it is possible to improve a cooling efficiency and also reduce pressure loss using a deep water channel with deep cavities. Furthermore, providing a plurality of cavities makes it possible to reduce a size of the power semiconductor modules and provide a plurality of power semiconductor modules, thus improving reliability. It is possible to place a control board below the water channel to thermally cut off the control board from the power semiconductor modules, which makes it possible to reduce temperature of a control circuit.

Abstract translation: 根据本发明，提供一种在壳体中形成多个浅空腔和深腔的水冷逆变器结构，将功率半导体模块的底表面固定到浅腔，以形成浅水通道并直接冷却功率半导体模块 使用这个浅水通道。 由于冷却水在浅水通道中快速流动，所以可以提高冷却效率，并且还可以使用具有深空腔的深水通道来减少压力损失。 此外，提供多个空腔使得可以减小功率半导体模块的尺寸并提供多个功率半导体模块，从而提高可靠性。 可以在水通道下方设置控制板，以将功率半导体模块的控制板热切断，从而可以降低控制电路的温度。

公开(公告)号：US4794445A

公开(公告)日：1988-12-27

申请号：US78999

申请日：1987-07-29

Applicant: Hideo Homma ,  Yutaka Misawa ,  Naohiro Momma

Inventor： Hideo Homma ,  Yutaka Misawa ,  Naohiro Momma

IPC: H01L29/73 ,  H01L21/20 ,  H01L21/331 ,  H01L21/74 ,  H01L21/762 ,  H01L29/732 ,  H01L23/08 ,  H01L23/54

CPC classification number: H01L21/2007 ,  H01L21/74 ,  H01L21/76264 ,  H01L21/76297 ,  H01L29/7325 ,  H01L21/76275 ,  H01L21/76281

Abstract: A semiconductor device has a structure in which two semiconductor substrates are coupled to each other through a semiconductor oxide film and a metal silicide film, and a semiconductor element, for example, a bi-polar transistor is formed in the semiconductor substrate on the metal silicide film side, whereby a metal silicide layer having a high melting point is provided beneath one region of the bi-polar transistor for example, an n.sup.+ buried collector layer and in ohmic contact with the n.sup.+ buried collector layer. An electrical isolation between the adjacent semiconductor elements is made by an insulating layer.

公开(公告)号：US4402001A

公开(公告)日：1983-08-30

申请号：US868791

申请日：1978-01-12

Applicant: Naohiro Momma ,  Hiroyuki Taniguchi

Inventor： Naohiro Momma ,  Hiroyuki Taniguchi

IPC: H01L29/73 ,  H01L21/223 ,  H01L21/331 ,  H01L29/08 ,  H01L29/10 ,  H01L29/36 ,  H01L29/74 ,  H01L29/861 ,  H01L29/06

CPC classification number: H01L29/102 ,  H01L21/223 ,  H01L29/0834 ,  H01L29/36 ,  Y10S438/904

Abstract: A semiconductor element such as a thyristor or a transistor which is capable of withstanding a high voltage comprises a semiconductor substrate of a pnpn-four layer structure (for a thyristor) or of a npn-three layer structure (for a transistor). An intermediate p-type layer is composed of a low concentration layer region located adjacent to an n-type layer and a high concentration layer region located adjacent to the other n-type layer. The high concentration layer region is formed through diffusion of aluminium so that the maximum concentration thereof becomes at least equal to 5.times.10.sup.16 atoms/cm.sup.3. A method of manufacturing such semiconductor element is also disclosed.

Abstract translation: 能够耐受高电压的诸如晶闸管或晶体管的半导体元件包括pnpn四层结构（晶闸管）或npn三层结构（用于晶体管）的半导体衬底。 中间p型层由与n型层相邻的低浓度层区域和与其他n型层相邻的高浓度层区域构成。 通过铝的扩散形成高浓度层区域，使其最大浓度至少等于5×10 16原子/ cm 3。 还公开了制造这种半导体元件的方法。

公开(公告)号：US5883403A

公开(公告)日：1999-03-16

申请号：US720017

申请日：1996-09-27

Applicant: Katsumi Ishikawa ,  Katsuaki Saito ,  Yutaka Sato ,  Atsuo Watanabe ,  Shuji Katoh ,  Naohiro Momma

Inventor： Katsumi Ishikawa ,  Katsuaki Saito ,  Yutaka Sato ,  Atsuo Watanabe ,  Shuji Katoh ,  Naohiro Momma

IPC: H01L29/32 ,  H01L29/74 ,  H01L31/111

CPC classification number: H01L29/74 ,  H01L29/32 ,  H01L29/861 ,  Y10S257/913

Abstract: In a semiconductor device, such as a diode and thyristor, having at least one pn junction between a pair of main surfaces, a first main electrode formed on the surface of one of the main surfaces and a second main electrode formed on the surface of the other one of the main surfaces, a semiconductor lattice defect is formed such that its lattice defect density increases gradually in the direction from the first main electrode to the second main electrode. Since the distribution of the carrier density in the conduction state can be flattened, the reverse recovery charge can be reduced substantially without causing the ON-state voltage to increase.

Abstract translation: 在诸如二极管和晶闸管之类的半导体器件中，在一对主表面之间具有至少一个pn结，形成在一个主表面的表面上的第一主电极和形成在主表面上的第二主电极 主表面中的另一个，形成半导体晶格缺陷，使得其晶格缺陷密度在从第一主电极到第二主电极的方向上逐渐增加。 由于载流子密度在导通状态下的分布可以变平，所以可以大大降低反向恢复电荷，而不会导致导通状态电压增加。

公开(公告)号：US5726488A

公开(公告)日：1998-03-10

申请号：US243325

申请日：1994-05-16

Applicant: Atsuo Watanabe ,  Yoshiaki Yazawa ,  Atsushi Hiraishi ,  Masataka Minami ,  Takahiro Nagano ,  Takahide Ikeda ,  Naohiro Momma

Inventor： Atsuo Watanabe ,  Yoshiaki Yazawa ,  Atsushi Hiraishi ,  Masataka Minami ,  Takahiro Nagano ,  Takahide Ikeda ,  Naohiro Momma

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/088 ,  H01L27/092 ,  H01L29/78 ,  H01L27/02

CPC classification number: H01L27/0623 ,  H01L21/8238 ,  H01L21/8249 ,  Y10S257/921

Abstract: A semiconductor device has a well region formed in the surface of a substrate, and has functional portions such as MOSFET and bipolar transistor formed in the well region. The carrier concentration profile of the well region assumes the shape of a valley in the direction of depth thereof, and a minimum point thereof has a concentration of smaller than 5.times.10.sup.15 cm.sup.-3 and is located at a position within 1.6 .mu.m from the surface of the substrate. Preferably, the minimum point should have a concentration of greater than 5.times.10.sup.14 cm.sup.-3 but smaller than 5.times.10.sup.15 cm.sup.-3, and more preferably a concentration of greater than 1.times.10.sup.15 cm.sup.-3 but smaller than 5.times.10.sup.15 cm.sup.-3.

Abstract translation: 半导体器件具有在衬底的表面中形成的阱区，并且具有形成在阱区中的诸如MOSFET和双极晶体管的功能部分。 阱区域的载流子浓度分布呈深谷方向的谷状，其最小点浓度小于5×10 15 cm -3，位于距离其表面1.6m以内的位置 底物。 优选地，最小点应该具有大于5×10 14 cm -3但小于5×10 15 cm -3的浓度，更优选大于1×10 15 cm -3但小于5×10 15 cm -3的浓度。