公开(公告)号：US06541336B1

公开(公告)日：2003-04-01

申请号：US10147248

申请日：2002-05-15

Applicant: Marc W. Cantell ,  Rajesh Chopdekar ,  Peter J. Geiss

Inventor： Marc W. Cantell ,  Rajesh Chopdekar ,  Peter J. Geiss

IPC: H01L218042

CPC classification number: H01L29/66287 ,  H01L29/0804

Abstract: A method of fabricating a bipolar transistor. The method comprising: forming an emitter opening in a dielectric layer to expose a surface of a base layer; performing a clean of the exposed surface, the clean removing any oxide present on the surface and passivating the surface to inhibit oxide growth; and forming an emitter layer on the surface after the performing a clean.

Abstract translation: 一种制造双极晶体管的方法。 该方法包括：在电介质层中形成发射极开口以露出基底层的表面; 清洁暴露的表面，清洁去除表面上存在的任何氧化物，钝化表面以抑制氧化物生长; 并且在执行清洁之后在表面上形成发射极层。

公开(公告)号：US06255179B1

公开(公告)日：2001-07-03

申请号：US09368212

申请日：1999-08-04

Applicant: Marc W. Cantell ,  Kenneth Giewont ,  Jerome B. Lasky ,  Kirk D. Peterson

Inventor： Marc W. Cantell ,  Kenneth Giewont ,  Jerome B. Lasky ,  Kirk D. Peterson

IPC: H01L21336

CPC classification number: H01L21/02054 ,  H01L21/28518

Abstract: A method of preparing silicon semiconductor surfaces prior to metal silicide formation. In particular, it teaches a method of treating about 10 to about 200 Å of a surface of the silicon with a plasma source after activating the source and drain regions, prior to an HF etch and deposition of a metal for silicide formation. Discontinuities in the metal silicide formed on narrow polysilicon lines at the point where source and drain regions intersect are surprisingly diminished. This results in more continuous, uniform silicide formation hence the polysilicon lines and the source and drain regions have substantially lower resistance.

Abstract translation: 在金属硅化物形成之前制备硅半导体表面的方法。 特别地，它教导了在HF蚀刻和用于硅化物形成的金属的沉积之前，在激活源极和漏极区域之后用等离子体源处理大约10至大约200的硅表面的方法。 在源极和漏极区相交的点处形成在窄多晶硅线上的金属硅化物的不连续性令人惊讶地减少。 这导致更连续，均匀的硅化物形成，因此多晶硅线路和源极和漏极区域具有显着较低的电阻。

公开(公告)号：US20120313146A1

公开(公告)日：2012-12-13

申请号：US13155730

申请日：2011-06-08

Applicant: Marc W. Cantell ,  Thai Doan ,  Jessica A. Levy ,  Qizhi Liu ,  William J. Murphy ,  Christa R. Willets

Inventor： Marc W. Cantell ,  Thai Doan ,  Jessica A. Levy ,  Qizhi Liu ,  William J. Murphy ,  Christa R. Willets

IPC: H01L29/737 ,  H01L21/331 ,  H01L29/73

CPC classification number: H01L29/66234 ,  H01L21/8222 ,  H01L29/0804 ,  H01L29/0817 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/7378

Abstract: Disclosed is a transistor structure, having a completely silicided extrinsic base for reduced base resistance Rb. Specifically, a metal silicide layer covers the extrinsic base, including the portion of the extrinsic base that extends below the upper portion of a T-shaped emitter. One exemplary technique for ensuring that the metal silicide layer covers this portion of the extrinsic base requires tapering the upper portion of the emitter. Such tapering allows a sacrificial layer below the upper portion of the emitter to be completely removed during processing, thereby exposing the extrinsic base below and allowing the metal layer required for silicidation to be deposited thereon. This metal layer can be deposited, for example, using a high pressure sputtering technique to ensure that all exposed surfaces of the extrinsic base, even those below the upper portion of the emitter, are covered.

Abstract translation: 公开了一种晶体管结构，具有完全硅化的外基，用于降低碱电阻Rb。 具体地说，金属硅化物层覆盖外部基体，包括在T形发射体的上部下方延伸的外部基底部分。 用于确保金属硅化物层覆盖外部基极的这一部分的一个示例性技术需要使发射极的上部逐渐变细。 这种锥形允许在处理期间完全去除发射器上部下方的牺牲层，从而将外部基底暴露在下面，并使硅化物所需的金属层沉积在其上。 例如，可以使用高压溅射技术来沉积该金属层，以确保外部基底的所有暴露表面，甚至覆盖在发射体上部以下的那些。

公开(公告)号：US07446007B2

公开(公告)日：2008-11-04

申请号：US11560893

申请日：2006-11-17

Applicant: James W. Adkisson ,  Marc W. Cantell ,  James R. Elliott ,  James V. Hart, III ,  Dale W. Martin

Inventor： James W. Adkisson ,  Marc W. Cantell ,  James R. Elliott ,  James V. Hart, III ,  Dale W. Martin

IPC: H01L21/336

CPC classification number: H01L29/4983 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659

Abstract: A semiconductor structure includes a multi-layer spacer located adjacent and adjoining a sidewall of a topographic feature within the semiconductor structure. The multi-layer spacer includes a first spacer sub-layer comprising a deposited silicon oxide material laminated to a second spacer sub-layer comprising a material that is other than the deposited silicon oxide material. The first spacer sub-layer is recessed with respect to the second spacer sub-layer by a recess distance of no greater than a thickness of the first spacer sub-layer (and preferably from about 50 to about 150 angstroms). Such a recess distance is realized through use of a chemical oxide removal (COR) etchant that is self limiting for the deposited silicon oxide material with respect to a thermally grown silicon oxide material. Dimensional integrity and delamination avoidance is thus assured for the multi-layer spacer layer.

Abstract translation: 半导体结构包括位于半导体结构内邻近并毗邻地形特征的侧壁的多层隔离物。 多层间隔物包括第一间隔子层，该第一间隔子层包含层叠到包含不同于沉积氧化硅材料的材料的第二间隔子层的沉积氧化硅材料。 第一间隔子层相对于第二间隔物子层凹陷凹陷距离不大于第一间隔子层的厚度（优选为约50至约150埃）。 通过使用相对于热生长的氧化硅材料对沉积的氧化硅材料来说是自限制的化学氧化物去除（COR）蚀刻剂来实现这种凹陷距离。 因此确保了多层间隔层的尺寸完整性和分层避免。

公开(公告)号：US06774000B2

公开(公告)日：2004-08-10

申请号：US10300239

申请日：2002-11-20

Applicant: Wesley C. Natzle ,  Marc W. Cantell ,  Louis D. Lanzerotti ,  Effendi Leobandung ,  Brian L. Tessier ,  Ryan W. Wuthrich

Inventor： Wesley C. Natzle ,  Marc W. Cantell ,  Louis D. Lanzerotti ,  Effendi Leobandung ,  Brian L. Tessier ,  Ryan W. Wuthrich

IPC: H01L21336

CPC classification number: H01L21/31116 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/28035 ,  H01L21/28114 ,  H01L21/28247 ,  H01L21/28525 ,  H01L21/28562 ,  H01L29/66628

Abstract: A process for manufacturing an FET device. A semiconductor substrate is covered with a gate dielectric layer and with a conductive gate electrode formed over the gate dielectric. Blanket layers of silicon oxide may be added. An optional collar of silicon nitride may be formed over the silicon oxide layer around the gate electrode. Two precleaning steps are performed. Chemical oxide removal gases are then deposited, covering the device with an adsorbed reactant film. The gate dielectric (aside from the gate electrode) is removed, as the adsorbed reactant film reacts with the gate dielectric layer to form a rounded corner of silicon oxide at the base of the gate electrode. One or two in-situ doped silicon layers are deposited over the source/drain regions to form single or laminated epitaxial raised source/drain regions over the substrate protruding beyond the surface of the gate dielectric.

公开(公告)号：US20080116493A1

公开(公告)日：2008-05-22

申请号：US11560893

申请日：2006-11-17

Applicant: James W. Adkisson ,  Marc W. Cantell ,  James R. Elliott ,  James V. Hart ,  Dale W. Martin

Inventor： James W. Adkisson ,  Marc W. Cantell ,  James R. Elliott ,  James V. Hart ,  Dale W. Martin

IPC: H01L21/28 ,  H01L29/78

CPC classification number: H01L29/4983 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659

Abstract: A semiconductor structure includes a multi-layer spacer located adjacent and adjoining a sidewall of a topographic feature within the semiconductor structure. The multi-layer spacer includes a first spacer sub-layer comprising a deposited silicon oxide material laminated to a second spacer sub-layer comprising a material that is other than the deposited silicon oxide material. The first spacer sub-layer is recessed with respect to the second spacer sub-layer by a recess distance of no greater than a thickness of the first spacer sub-layer (and preferably from about 50 to about 150 angstroms). Such a recess distance is realized through use of a chemical oxide removal (COR) etchant that is self limiting for the deposited silicon oxide material with respect to a thermally grown silicon oxide material. Dimensional integrity and delamination avoidance is thus assured for the multi-layer spacer layer.

Abstract translation: 半导体结构包括位于半导体结构内邻近并毗邻地形特征的侧壁的多层隔离物。 多层间隔物包括第一间隔子层，该第一间隔子层包含层叠到包含不同于沉积氧化硅材料的材料的第二间隔子层的沉积氧化硅材料。 第一间隔子层相对于第二间隔物子层凹陷凹陷距离不大于第一间隔子层的厚度（优选为约50至约150埃）。 通过使用相对于热生长的氧化硅材料对沉积的氧化硅材料来说是自限制的化学氧化物去除（COR）蚀刻剂来实现这种凹陷距离。 因此确保了多层间隔层的尺寸完整性和分层避免。

公开(公告)号：US06900519B2

公开(公告)日：2005-05-31

申请号：US10865138

申请日：2004-06-10

Applicant: Marc W. Cantell ,  James S. Dunn ,  David L. Harame ,  Robb A. Johnson ,  Louis D. Lanzerotti ,  Stephen A. St. Onge ,  Brian L. Tessier ,  Ryan W. Wuthrich

Inventor： Marc W. Cantell ,  James S. Dunn ,  David L. Harame ,  Robb A. Johnson ,  Louis D. Lanzerotti ,  Stephen A. St. Onge ,  Brian L. Tessier ,  Ryan W. Wuthrich

IPC: H01L21/331 ,  H01L21/8249 ,  H01L29/10 ,  H01L27/082

CPC classification number: H01L29/66287 ,  H01L21/8249 ,  H01L29/1004

Abstract: The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance by providing reduced base resistence. The preferred design forms the extrinsic base by diffusing dopants from a dopant source layer and into the extrinsic base region. This diffusion of dopants forms at least a portion of the extrinsic base. In particular, the portion adjacent to the intrinsic base region is formed by diffusion. This solution avoids the problems caused by traditional solutions that implanted the extrinsic base. Specifically, by forming at least a portion of the extrinsic base by diffusion, the problem of damage to base region is minimized. This reduced damage enhances dopant diffusion into the intrinsic base. Additionally, the formed extrinsic base can have improved resistence, resulting in an improved maximum frequency for the bipolar device. Additionally, the extrinsic base can be formed with a self-aligned manufacturing process that reduces fabrication complexity.

公开(公告)号：US06858532B2

公开(公告)日：2005-02-22

申请号：US10316211

申请日：2002-12-10

Applicant: Wesley C. Natzle ,  David C. Ahlgren ,  Steven G. Barbee ,  Marc W. Cantell ,  Basanth Jagannathan ,  Louis D. Lanzerotti ,  Seshadri Subbanna ,  Ryan W. Wuthrich

Inventor： Wesley C. Natzle ,  David C. Ahlgren ,  Steven G. Barbee ,  Marc W. Cantell ,  Basanth Jagannathan ,  Louis D. Lanzerotti ,  Seshadri Subbanna ,  Ryan W. Wuthrich

IPC: H01L21/302 ,  H01L21/311 ,  H01L21/331 ,  H01L21/8249 ,  H01L29/732 ,  H01L21/4763

CPC classification number: H01L29/66242 ,  H01L21/31116 ,  H01L21/8249

Abstract: An oxide etch process is described which may be used for emitter and base preparation in bipolar SiGe devices. The low temperature process employed produces electrical insulation between the emitter and base by a COR etch which preserves insulating TEOS glass. The insulating TEOS glass provides reduced capacitance and helps to achieve high speed. An apparatus is also described for practicing the disclosed process.

Abstract translation: 描述了氧化物蚀刻工艺，其可用于双极SiGe器件中的发射极和基极准备。 所采用的低温工艺通过保留绝缘TEOS玻璃的COR蚀刻产生发射极和基极之间的电绝缘。 绝缘TEOS玻璃提供降低的电容并有助于实现高速度。 还描述了用于实施所公开的方法的装置。

公开(公告)号：US06184132B2

公开(公告)日：2001-02-06

申请号：US09365859

申请日：1999-08-03

Applicant: Marc W. Cantell ,  Jerome B. Lasky ,  Ronald J. Line ,  William J. Murphy ,  Kirk D. Peterson ,  Prabhat Tiwari

Inventor： Marc W. Cantell ,  Jerome B. Lasky ,  Ronald J. Line ,  William J. Murphy ,  Kirk D. Peterson ,  Prabhat Tiwari

IPC: H01L2144

CPC classification number: H01L21/28518 ,  Y10S414/139 ,  Y10S438/906 ,  Y10S438/908

Abstract: A method and apparatus are provided for forming a silicide on a semiconductor substrate by integrating under a constant vacuum the processes of removing an oxide from a surface of a semiconductor substrate and depositing a metal on the cleaned surface without exposing the cleaned surface to air. The method and apparatus of the present invention eliminates the exposure of the cleaned substrate to air between the oxide removal and metal deposition steps. This in-situ cleaning of the silicon substrate prior to cobalt deposition provides a cleaner silicon substrate surface, resulting in enhanced formation of cobalt silicide when the cobalt layer is annealed.

公开(公告)号：US06926843B2

公开(公告)日：2005-08-09

申请号：US09727139

申请日：2000-11-30

Applicant: Marc W. Cantell ,  Wesley Natzle ,  Steven M. Ruegsegger

Inventor： Marc W. Cantell ,  Wesley Natzle ,  Steven M. Ruegsegger

IPC: H01L21/28 ,  H01L21/3213 ,  H01L21/00

CPC classification number: H01L21/32135 ,  H01L21/28123 ,  H01L21/32139

Abstract: Lines are fabricated by patterning a hard mask to provide a line segment, the line segment having a first dimension measured across the line segment; reacting a surface layer of the line segment to form a layer of a reaction product on a remaining portion of the line segment; and removing the reaction product without attacking the remaining portion of the line segment and without attacking the substrate to form the line segment with a dimension across the line segment that is smaller than the first dimension.

Abstract translation: 线通过图案化硬掩模以提供线段来制造，线段具有跨越线段测量的第一尺寸; 使所述线段的表面层反应以在所述线段的剩余部分上形成反应产物层; 并且除去反应产物而不攻击线段的剩余部分，而不攻击基底以形成具有小于第一尺寸的线段上的尺寸的线段。