公开(公告)号：US10437468B2

公开(公告)日：2019-10-08

申请号：US15098324

申请日：2016-04-14

Applicant: Feng-Yi Yu ,  Chia-Shin Weng ,  Hsin-Pei Tsai ,  Jih-Houng Lee ,  Kuan-Yu Chen

Inventor： Feng-Yi Yu ,  Chia-Shin Weng ,  Hsin-Pei Tsai ,  Jih-Houng Lee ,  Kuan-Yu Chen

IPC: G06F3/0483 ,  G06F3/0481 ,  G06F3/0488 ,  G06F3/041 ,  G06F3/147 ,  G06F3/0489 ,  G06F3/0484 ,  G09G5/14

Abstract: An electronic apparatus and an operating method of the electronic apparatus are provided. The electronic apparatus includes a display unit, a base, a touch pad and a processing unit. The base is coupled to the display unit. The touch pad is disposed on the base, includes touch areas and receives a touch action performed by the user on any touch area. The processing unit is coupled to the touch pad and sets a display frame of the display unit into display areas according to a position of each touch area, so that each touch area has the corresponding display area at a corresponding position on the display unit. After the touch pad received a first touch event, the processing unit obtains a first touch area where the first touch event is generated, and displays a first user interface in a first display area corresponding to the first touch area.

公开(公告)号：US09391378B2

公开(公告)日：2016-07-12

申请号：US13996004

申请日：2011-12-23

Applicant: Michael Leddige ,  Yun Ling ,  Kuan-Yu Chen ,  Kai Wang ,  Xiang Li ,  Howard Heck

Inventor： Michael Leddige ,  Yun Ling ,  Kuan-Yu Chen ,  Kai Wang ,  Xiang Li ,  Howard Heck

IPC: H01R4/48 ,  H01R12/72 ,  H01R13/24 ,  H01R12/71 ,  H01R43/18 ,  H01R13/66

CPC classification number: H01R4/48 ,  H01R12/71 ,  H01R12/716 ,  H01R12/721 ,  H01R13/24 ,  H01R13/6658 ,  H01R43/18 ,  Y10T29/49208

Abstract: Methods and systems to support input output (IO) communications may include an IO connector having a housing with surfaces defining a paddle card region, and a set of compressible contacts extending vertically through the housing into the paddle card region. In addition, an IO interconnect can include a cable portion and at least one end portion coupled to the cable portion. The end portion may include a paddle card having a circuit board with a set of contacts disposed on a bottom surface of the circuit board. The end portion can also include an asymmetric metal shell having a configuration that encloses at least a portion of the paddle card and exposes the set of contacts.

Abstract translation: 支持输入输出（IO）通信的方法和系统可以包括具有壳体的IO连接器，所述壳体具有限定桨卡区域的表面，以及一组垂直延伸穿过壳体进入桨卡区域的可压缩触点。 此外，IO互连可以包括电缆部分和耦合到电缆部分的至少一个端部部分。 端部可以包括具有电路板的桨卡，该电路板具有布置在电路板的底表面上的一组触点。 端部部分还可以包括不对称的金属壳体，该壳体具有包围桨片的至少一部分并且暴露该组触点的构造。

公开(公告)号：US20130335394A1

公开(公告)日：2013-12-19

申请号：US13585858

申请日：2012-08-15

Applicant: Bo-Jhang Sun ,  Chin-Hai Huang ,  Kuan-Yu Chen ,  Szu-Chi Huang

Inventor： Bo-Jhang Sun ,  Chin-Hai Huang ,  Kuan-Yu Chen ,  Szu-Chi Huang

IPC: G06F3/038

CPC classification number: G09G3/3233 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2320/043

Abstract: A driving circuit of an organic light emitting device includes a switch module, a capacitor, and a driving unit. The switch module includes a first switch unit and a second switch unit. The first switch unit is coupled to a data line. The second switch unit is coupled to the organic light emitting device. During a programming period, the first switch unit is turned on and the second switch unit is turned off; and during an emission period, the first switch unit is turned off and the second switch unit is turned on. The capacitor is coupled to the first switch unit for being charged to a data voltage according to a data current of the data line during the programming period. The driving unit is used for generating a driving current to drive the organic light emitting device according to the data voltage during the emission period.

Abstract translation: 有机发光器件的驱动电路包括开关模块，电容器和驱动单元。 开关模块包括第一开关单元和第二开关单元。 第一开关单元耦合到数据线。 第二开关单元耦合到有机发光器件。 在编程期间，第一开关单元导通，第二开关单元断开; 并且在发光期间，关闭第一开关单元并接通第二开关单元。 电容器耦合到第一开关单元，用于在编程周期期间根据数据线的数据电流将其充电到数据电压。 驱动单元用于产生驱动电流，以在发光期间根据数据电压驱动有机发光器件。

公开(公告)号：US08558289B2

公开(公告)日：2013-10-15

申请号：US12795088

申请日：2010-06-07

Applicant: Chun-Fai Cheng ,  Hsueh-Chang Sung ,  Kuan-Yu Chen ,  Hsien-Hsin Lin ,  Fung Ka Hing

Inventor： Chun-Fai Cheng ,  Hsueh-Chang Sung ,  Kuan-Yu Chen ,  Hsien-Hsin Lin ,  Fung Ka Hing

IPC: H01L29/76 ,  H01L21/336

CPC classification number: H01L29/7848 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

Abstract: A transistor includes a gate electrode disposed over a substrate. At least one composite strain structure is disposed adjacent to a channel below the gate electrode. The at least one composite strain structure includes a first strain region within the substrate. A second strain region is disposed over the first strain region. At least a portion of the second strain region is disposed within the substrate.

Abstract translation: 晶体管包括设置在衬底上的栅电极。 至少一个复合应变结构邻近栅电极下方的沟道设置。 所述至少一个复合应变结构包括所述基底内的第一应变区。 第二应变区设置在第一应变区上。 第二应变区域的至少一部分设置在衬底内。

公开(公告)号：US08493168B2

公开(公告)日：2013-07-23

申请号：US13222231

申请日：2011-08-31

Applicant: Ming-Fan Tsai ,  Kuan-Yu Chen ,  Bo-Shiang Fang ,  Hsin-Hung Lee

Inventor： Ming-Fan Tsai ,  Kuan-Yu Chen ,  Bo-Shiang Fang ,  Hsin-Hung Lee

IPC: H01F5/00 ,  H01F27/28

CPC classification number: H01F17/0006 ,  H01F19/00

Abstract: An asymmetric differential inductor includes first and second conductive wirings spirally disposed on a substrate having a first input terminal, a second input terminal, a ground terminal, and a central conductive wiring. The central conductive wiring has a central contact connecting the ground terminal and a central end away from the ground terminal. The first conductive wiring extends across the central conductive wiring and has a first contact connecting the first input terminal and a first end connecting the central end. The second conductive wiring extends across the central conductive wiring and interlaces with the first conductive wiring and has a second contact connecting the second input terminal and a second end connecting the central end. Corresponding portions of wiring sections of the first and second conductive wirings at opposite sides of the central conductive wiring are asymmetrical to one another to thereby save substrate space and facilitate circuit layout.

Abstract translation: 非对称差分电感器包括螺旋地设置在具有第一输入端子，第二输入端子，接地端子和中心导电布线的基板上的第一和第二导电布线。 中心导电布线具有连接接地端子和远离接地端子的中心端的中心接触点。 第一导电布线延伸穿过中心导电布线，并且具有连接第一输入端和连接中心端的第一端的第一触点。 所述第二导电布线延伸穿过所述中心导电布线并与所述第一导电布线交织，并且具有连接所述第二输入端子和连接所述中心端部的第二端部的第二触点。 在中心导电布线的相对侧的第一和第二导电布线的布线部分的相应部分彼此不对称，从而节省基板空间并且便于布线。

公开(公告)号：US08487354B2

公开(公告)日：2013-07-16

申请号：US12545705

申请日：2009-08-21

Applicant: Kuan-Yu Chen ,  Hsien-Hsin Lin ,  Chun-Feng Nieh ,  Hsueh-Chang Sung ,  Chien-Chang Su ,  Tsz-Mei Kwok

Inventor： Kuan-Yu Chen ,  Hsien-Hsin Lin ,  Chun-Feng Nieh ,  Hsueh-Chang Sung ,  Chien-Chang Su ,  Tsz-Mei Kwok

IPC: H01L29/76

CPC classification number: H01L29/66477 ,  H01L21/31116 ,  H01L21/31155 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7848

Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a gate structure over the substrate, forming a material layer over the substrate and the gate structure, implanting Ge, C, P, F, or B in the material layer, removing portions of the material layer overlying the substrate at either side of the gate structure, forming recesses in the substrate at either side of the gate structure, and depositing a semiconductor material in the recesses by an expitaxy process.

Abstract translation: 本公开提供一种制造半导体器件的方法，其包括提供半导体衬底，在衬底上形成栅极结构，在衬底上形成材料层和栅极结构，将Ge，C，P，F或B注入 所述材料层，去除所述栅极结构的任一侧上覆盖所述衬底的所述材料层的部分，在所述栅极结构的任一侧上在所述衬底中形成凹陷，以及通过开晶过程在所述凹部中沉积半导体材料。

公开(公告)号：US08344447B2

公开(公告)日：2013-01-01

申请号：US11732889

申请日：2007-04-05

Applicant: Hsien-Hsin Lin ,  Weng Chang ,  Chien-Chang Su ,  Kuan-Yu Chen ,  Hsueh-Chang Sung ,  Ming-Hua Yu

Inventor： Hsien-Hsin Lin ,  Weng Chang ,  Chien-Chang Su ,  Kuan-Yu Chen ,  Hsueh-Chang Sung ,  Ming-Hua Yu

IPC: H01L29/94

CPC classification number: H01L29/66477 ,  H01L21/02532 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: A composite semiconductor structure and method of forming the same are provided. The composite semiconductor structure includes a first silicon-containing compound layer comprising an element selected from the group consisting essentially of germanium and carbon; a silicon layer on the first silicon-containing compound layer, wherein the silicon layer comprises substantially pure silicon; and a second silicon-containing compound layer comprising the element on the silicon layer. The first and the second silicon-containing compound layers have substantially lower silicon concentrations than the silicon layer. The composite semiconductor structure may be formed as source/drain regions of metal-oxide-semiconductor (MOS) devices.

Abstract translation: 提供一种复合半导体结构及其形成方法。 复合半导体结构包括第一含硅化合物层，其包含选自基本上由锗和碳组成的组的元素; 所述第一含硅化合物层上的硅层，其中所述硅层包含基本上纯的硅; 以及在所述硅层上包含所述元素的第二含硅化合物层。 第一和第二含硅化合物层具有比硅层低的硅浓度。 复合半导体结构可以形成为金属氧化物半导体（MOS）器件的源极/漏极区域。

公开(公告)号：US08305182B1

公开(公告)日：2012-11-06

申请号：US13243138

申请日：2011-09-23

Applicant: Ming-Fan Tsai ,  Kuan-Yu Chen ,  Bo-Shiang Fang ,  Hsin-Hung Lee

Inventor： Ming-Fan Tsai ,  Kuan-Yu Chen ,  Bo-Shiang Fang ,  Hsin-Hung Lee

IPC: H01F5/00 ,  H01F27/28

CPC classification number: H01L23/5227 ,  H01F19/04 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A symmetric differential inductor structure includes first, second, third and fourth spiral conductive wirings disposed in four quadrants of a substrate, respectively. Further, a fifth conductive wiring connects the first and fourth spiral conductive wirings, and a sixth conductive wiring connects the second and third spiral conductive wirings. The first and second spiral conductive wirings are symmetric but not intersected with one another, and the third and fourth spiral conductive wirings are symmetric but not intersected with one another. Therefore, the invention attains full geometric symmetry to avoid using conductive wirings that occupy a large area of the substrate as in the prior art and to thereby increase the product profit and yield.

Abstract translation: 对称差分电感器结构包括分别设置在基板的四个象限内的第一，第二，第三和第四螺旋导电布线。 此外，第五导电布线连接第一和第四螺旋导电布线，并且第六导电布线连接第二和第三螺旋导电布线。 第一和第二螺旋导电布线是对称的，但是彼此不相交，第三和第四螺旋导电布线是对称的但彼此不相交。 因此，本发明获得完全的几何对称性，以避免如现有技术那样使用占据基板的大面积的导电布线，从而提高产品利润和产量。

公开(公告)号：US20120248431A1

公开(公告)日：2012-10-04

申请号：US13183838

申请日：2011-07-15

Applicant: Ya-Huei HUANG ,  Kuan-Yu Chen ,  Ying-Hui Chen ,  Te-Yu Chen

Inventor： Ya-Huei HUANG ,  Kuan-Yu Chen ,  Ying-Hui Chen ,  Te-Yu Chen

IPC: H01L29/786

CPC classification number: H01L27/1225

Abstract: A transistor array substrate includes a substrate, a plurality of scan lines, a plurality of data lines and a plurality of pixel units. The scan lines and the data lines are all disposed on the substrate. Each pixel unit includes a transistor and a pixel electrode. The transistor is electrically connected to the pixel electrodes, the scan lines and the data lines. Each transistor includes a gate, a drain, a source, a metal-oxide-semiconductor layer and a channel protective layer. A channel gap exists between the drain and the source. The metal-oxide-semiconductor layer has a pair of side edges opposite to each other and the side edges are located at two ends of the channel gap. The channel protective layer covers the metal-oxide-semiconductor layer in the channel gap and protrudes from the side edges of the metal-oxide-semiconductor layer.

Abstract translation: 晶体管阵列基板包括基板，多条扫描线，多条数据线和多个像素单元。 扫描线和数据线都设置在基板上。 每个像素单元包括晶体管和像素电极。 晶体管电连接到像素电极，扫描线和数据线。 每个晶体管包括栅极，漏极，源极，金属氧化物半导体层和沟道保护层。 漏极和源极之间存在沟道间隙。 金属氧化物半导体层具有彼此相对的一对侧边缘，并且侧边缘位于沟道间隙的两端。 沟道保护层覆盖沟道间隙中的金属氧化物半导体层，并从金属氧化物半导体层的侧边缘突出。

公开(公告)号：US08263451B2

公开(公告)日：2012-09-11

申请号：US12713573

申请日：2010-02-26

Applicant: Chien-Chang Su ,  Tsz-Mei Kwok ,  Hsien-Hsin Lin ,  Hsueh-Chang Sung ,  Yi-Fang Pai ,  Kuan-Yu Chen

Inventor： Chien-Chang Su ,  Tsz-Mei Kwok ,  Hsien-Hsin Lin ,  Hsueh-Chang Sung ,  Yi-Fang Pai ,  Kuan-Yu Chen

IPC: H01L21/336 ,  H01L21/8234

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/785

Abstract: A method of forming an integrated circuit structure includes providing a wafer including a substrate and a semiconductor fin at a major surface of the substrate, and performing a deposition step to epitaxially grow an epitaxy layer on a top surface and sidewalls of the semiconductor fin, wherein the epitaxy layer includes a semiconductor material. An etch step is then performed to remove a portion of the epitaxy layer, with a remaining portion of the epitaxy layer remaining on the top surface and the sidewalls of the semiconductor fin.

Abstract translation: 一种形成集成电路结构的方法包括在衬底的主表面上提供包括衬底和半导体鳍片的晶片，并且执行沉积步骤以在半导体鳍片的顶表面和侧壁上外延生长外延层，其中 外延层包括半导体材料。 然后执行蚀刻步骤以去除外延层的一部分，其中外延层的剩余部分保留在半导体鳍片的顶表面和侧壁上。