公开(公告)号：US20070170521A1

公开(公告)日：2007-07-26

申请号：US11306827

申请日：2006-01-12

申请人： Wagdi Abadeer ,  Jeffrey Brown ,  Kiran Chatty ,  Robert Gauthier ,  Jed Rankin ,  William Tonti

发明人： Wagdi Abadeer ,  Jeffrey Brown ,  Kiran Chatty ,  Robert Gauthier ,  Jed Rankin ,  William Tonti

IPC分类号： H01L29/76

CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/1211

摘要： Disclosed is an integrated circuit with multiple semiconductor fins having different widths and variable spacing on the same substrate. The method of forming the circuit incorporates a sidewall image transfer process using different types of mandrels. Fin thickness and fin-to-fin spacing are controlled by an oxidation process used to form oxide sidewalls on the mandrels, and more particularly, by the processing time and the use of intrinsic, oxidation-enhancing and/or oxidation-inhibiting mandrels. Fin thickness is also controlled by using sidewalls spacers combined with or instead of the oxide sidewalls. Specifically, images of the oxide sidewalls alone, images of sidewall spacers alone, and/or combined images of sidewall spacers and oxide sidewalls are transferred into a semiconductor layer to form the fins. The fins with different thicknesses and variable spacing can be used to form a single multiple-fin FET or, alternatively, various single-fin and/or multiple-fin FETs.

公开(公告)号：US20070097570A1

公开(公告)日：2007-05-03

申请号：US11614659

申请日：2006-12-21

申请人： Kiran CHATTY ,  Robert GAUTHIER ,  Mahmoud MOUSA ,  Mujahid MUHAMMAD ,  Christopher PUTNAM

发明人： Kiran CHATTY ,  Robert GAUTHIER ,  Mahmoud MOUSA ,  Mujahid MUHAMMAD ,  Christopher PUTNAM

IPC分类号： H02H9/00

CPC分类号： H01L27/0266 ,  H03K17/08142

摘要： Method and device for protecting against electrostatic discharge. The method includes configuring a gate of at least one upper transistor of a transistor network connected between power rails to be biased to a prescribed value, and coupling an electrostatic discharge event to a gate of a lower transistor of the transistor network. The at least one upper and at least one lower transistors of the transistor network are respectively coupled between the power rails from a higher voltage to a lower voltage.

摘要翻译： 防止静电放电的方法和装置。 该方法包括配置连接在电源轨之间的晶体管网络的至少一个上晶体管的栅极以被偏置到规定值，以及将静电放电事件耦合到晶体管网络的下晶体管的栅极。 晶体管网络的至少一个上部和至少一个下部晶体管分别从较高电压到较低电压耦合在电源轨之间。

公开(公告)号：US20060157799A1

公开(公告)日：2006-07-20

申请号：US10905682

申请日：2005-01-17

申请人： Kiran Chatty ,  Robert Gauthier ,  Terence Hook ,  Christopher Putnam ,  Mujahid Muhammad

发明人： Kiran Chatty ,  Robert Gauthier ,  Terence Hook ,  Christopher Putnam ,  Mujahid Muhammad

IPC分类号： H01L29/76

CPC分类号： H01L29/78 ,  H01L27/027

摘要： A field effect transistor with associated parasitic lateral npn bipolar junction transistor includes a source region in a substrate, a channel region in the substrate laterally adjacent to the source region, a drain region in the substrate laterally adjacent to the channel region, and a gate above the channel region of the substrate. In addition, a reduced trigger voltage region of the substrate is positioned below the drain region. The reduced trigger voltage region has a threshold voltage of about zero and comprises an undoped region of the pure wafer substrate. Thus, the reduced trigger voltage region is free of implanted N-type and P-type doping.

摘要翻译： 具有相关联的寄生横向npn双极结型晶体管的场效应晶体管包括衬底中的源极区域，与源极区域横向相邻的衬底中的沟道区域，衬底中的与沟道区域横向相邻的漏极区域，以及位于 衬底的沟道区域。 此外，衬底的降低的触发电压区域位于漏极区域的下方。 降低的触发电压区域具有约零的阈值电压，并且包括纯晶片衬底的未掺杂区域。 因此，降低的触发电压区域没有注入的N型和P型掺杂。

公开(公告)号：US08884270B2

公开(公告)日：2014-11-11

申请号：US13436159

申请日：2012-03-30

申请人： Janna Casady ,  Jeffrey Casady ,  Kiran Chatty ,  David Sheridan ,  Andrew Ritenour

发明人： Janna Casady ,  Jeffrey Casady ,  Kiran Chatty ,  David Sheridan ,  Andrew Ritenour

IPC分类号： H01L29/06 ,  H01L29/808 ,  H01L29/40 ,  H01L29/66

CPC分类号： H01L29/8083 ,  H01L29/1608 ,  H01L29/402 ,  H01L29/66909

摘要： Vertical junction field effect transistors (VJFETs) having improved heat dissipation at high current flow while maintaining the desirable specific on-resistance and normalized saturated drain current properties characteristic of devices having small pitch lengths are described. The VJFETs comprise one or more electrically active source regions in electrical contact with the source metal of the device and one or more electrically inactive source regions not in electrical contact with the source metal of the device. The electrically inactive source regions dissipate heat generated by the electrically active source regions during current flow.

摘要翻译： 描述了在高电流下具有改进的散热的垂直结型场效应晶体管（VJFET），同时保持了具有小间距长度的器件所需的特定导通电阻和归一化饱和漏极电流特性。 VJFET包括与器件的源极金属电接触的一个或多个电活性源极区域和不与器件的源极金属电接触的一个或多个不活跃电源区域。 电流不稳定的源区域在电流流动期间耗散由电活性源区域产生的热量。

公开(公告)号：US20070127172A1

公开(公告)日：2007-06-07

申请号：US11275058

申请日：2005-12-06

申请人： Wagdi Abadeer ,  James Adkisson ,  Jeffrey Brown ,  Kiran Chatty ,  Robert Gauthier ,  Michael Hauser ,  Jed Rankin ,  William Tonti

发明人： Wagdi Abadeer ,  James Adkisson ,  Jeffrey Brown ,  Kiran Chatty ,  Robert Gauthier ,  Michael Hauser ,  Jed Rankin ,  William Tonti

IPC分类号： H02H9/00

CPC分类号： H01L23/5256 ,  H01L23/525 ,  H01L27/14609 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a method of executing an electrical function, such as a fusing operation, by activation through a chip embedded photodiode through spectrally selected external light activation, and corresponding structure and circuit. The present invention is based on having incident light with specific intensity/wave length characteristics, in conjunction with additional circuit elements to an integrated circuit, perform the implementation of repairs, i.e., replacing failing circuit elements with redundant ones for yield and/or reliability. Also to perform disconnection of ESD protection device from input pad once the packaged chip is placed in system. No additional pins on the package are necessary.

摘要翻译： 公开了通过光谱选择的外部光激活通过芯片嵌入式光电二极管的激活以及相应的结构和电路来执行诸如定影操作之类的电功能的方法。 本发明基于将具有特定强度/波长特性的入射光结合到集成电路的附加电路元件，执行维修的实现，即用冗余电路替换故障电路元件以获得和/或可靠性。 一旦封装的芯片放置在系统中，也可以将ESD保护装置从输入焊盘断开。 不需要额外的引脚。

公开(公告)号：US20060091951A1

公开(公告)日：2006-05-04

申请号：US10904238

申请日：2004-10-29

申请人： Wagdi Abadeer ,  Anthony Bonaccio ,  Kiran Chatty ,  John Fifield

发明人： Wagdi Abadeer ,  Anthony Bonaccio ,  Kiran Chatty ,  John Fifield

IPC分类号： H03F3/45 ,  H03F3/16

CPC分类号： H03F3/16 ,  H03F3/45179 ,  H03F3/505 ,  H03F2203/45468

摘要： An integrated circuit amplifier includes, in an exemplary embodiment, a first field effect transistor (FET) device configured as a source follower and a second FET device configured as a tunneling gate FET, the tunneling gate FET coupled to the source follower. The tunneling gate FET is further configured so as to set a transconductance of the amplifier and the source follower is configured so as to set an output conductance of the amplifier.

摘要翻译： 在示例性实施例中，集成电路放大器包括被配置为源极跟随器的第一场效应晶体管（FET）器件和被配置为隧道栅极FET的第二FET器件，所述隧道栅极FET耦合到源极跟随器。 隧道栅极FET进一步配置为设置放大器的跨导，并且配置源极跟随器以便设置放大器的输出电导。

公开(公告)号：US20050227418A1

公开(公告)日：2005-10-13

申请号：US10708912

申请日：2004-03-31

申请人： Kiran Chatty ,  Robert Gauthier ,  Mujahid Muhammad ,  Christopher Putnam

发明人： Kiran Chatty ,  Robert Gauthier ,  Mujahid Muhammad ,  Christopher Putnam

IPC分类号： H01L21/329 ,  H01L21/84 ,  H01L27/02 ,  H01L27/12 ,  H01L29/861

CPC分类号： H01L27/0255 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66136 ,  H01L29/861

摘要： A method of forming a self-aligned SOI diode, the method comprising depositing a protective structure over a substrate; implanting a plurality of diffusion regions of variable dopant types in an area between at least one pair of isolation regions in the substrate, the plurality of diffusion regions separated by a diode junction, wherein the implanting aligns an upper surface of the diode junction with the protective structure; and removing the protective structure. The method further comprises forming a silicide layer over the diffusion regions and aligned with the protective structure. The protective structure comprises a hard mask, wherein the hard mask comprises a silicon nitride layer. Alternatively, the protective structure comprises a polysilicon gate and insulating spacers on opposite sides of the gate. Furthermore, in the removing step, the spacers remain on the substrate.

摘要翻译： 一种形成自对准SOI二极管的方法，所述方法包括在衬底上沉积保护结构; 在衬底中的至少一对隔离区域之间的区域中注入多个可变掺杂剂类型的扩散区域，所述多个扩散区域被二极管结点隔开，其中所述注入将所述二极管结的上表面与所述保护层 结构体; 并移除保护结构。 该方法还包括在扩散区上形成硅化物层并与保护结构对准。 保护结构包括硬掩模，其中硬掩模包括氮化硅层。 或者，保护结构包括在栅极的相对侧上的多晶硅栅极和绝缘间隔物。 此外，在去除步骤中，衬垫保留在衬底上。

公开(公告)号：US20070284669A1

公开(公告)日：2007-12-13

申请号：US11838934

申请日：2007-08-15

申请人： Wagdi Abadeer ,  Jeffrey Brown ,  Kiran Chatty ,  Robert Gauthier ,  Jed Rankin ,  William Tonti

发明人： Wagdi Abadeer ,  Jeffrey Brown ,  Kiran Chatty ,  Robert Gauthier ,  Jed Rankin ,  William Tonti

IPC分类号： H01L29/76

CPC分类号： B07C5/344 ,  G01R31/2831

摘要： Disclosed is an integrated circuit with multiple semiconductor fins having different widths and variable spacing on the same substrate. The method of forming the circuit incorporates a sidewall image transfer process using different types of mandrels. Fin thickness and fin-to-fin spacing are controlled by an oxidation process used to form oxide sidewalls on the mandrels, and more particularly, by the processing time and the use of intrinsic, oxidation-enhancing and/or oxidation-inhibiting mandrels. Fin thickness is also controlled by using sidewalls spacers combined with or instead of the oxide sidewalls. Specifically, images of the oxide sidewalls alone, images of sidewall spacers alone, and/or combined images of sidewall spacers and oxide sidewalls are transferred into a semiconductor layer to form the fins. The fins with different thicknesses and variable spacing can be used to form a single multiple-fin FET or, alternatively, various single-fin and/or multiple-fin FETs.

公开(公告)号：US20070210387A1

公开(公告)日：2007-09-13

申请号：US11370369

申请日：2006-03-08

申请人： Cornelius Russ ,  David Alvarez ,  Kiran Chatty ,  Jens Schneider ,  Robert Gauthier ,  Martin Wendel

发明人： Cornelius Russ ,  David Alvarez ,  Kiran Chatty ,  Jens Schneider ,  Robert Gauthier ,  Martin Wendel

IPC分类号： H01L23/62

CPC分类号： H01L29/78 ,  H01L29/0626 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/456

摘要： An ESD protection device includes a source region, a channel region adjacent the source region, and an elongated drain region spaced from the source region by the channel region. The elongated drain region includes an unsilicided portion adjacent the channel and a silicided portion spaced from channel region by the unsilicided portion. A first ESD region is located beneath the silicided portion of the elongated drain region and a second ESD region is located beneath the unsilicided portion of the elongated drain region, the second ESD region being spaced from the first ESD region.

摘要翻译： ESD保护器件包括源极区域，与源极区域相邻的沟道区域以及由沟道区域与源极区域间隔开的细长漏极区域。 细长的漏极区域包括邻近通道的非硅化部分和通过非硅化部分与沟道区域隔开的硅化部分。 第一ESD区域位于细长漏区域的硅化部分下方，第二ESD区域位于细长漏区域的未硅化部分的下方，第二ESD区域与第一ESD区域间隔开。

公开(公告)号：US20050224882A1

公开(公告)日：2005-10-13

申请号：US10709041

申请日：2004-04-08

申请人： Kiran Chatty ,  Robert Gauthier ,  Mujahid Muhammad ,  Christopher Putnam

发明人： Kiran Chatty ,  Robert Gauthier ,  Mujahid Muhammad ,  Christopher Putnam

IPC分类号： H01L23/62 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/78 ,  H01L29/0653 ,  H01L29/1083 ,  H01L2924/0002 ,  H01L2924/00

摘要： An ESD NMOSFET, and a method for lowering a ESD NMOSFET trigger voltage. An ESD NMOSFET is configured in triple well CMOS architecture where the first well is separated from second and third wells by respective shallow well isolation regions. The first well is also separated from the substrate along the bottom by a conductive band region. A substrate contact is located outside of the first, second and third wells, and provides a current path during an ESD event from the first well. Source and drain regions are formed in the first well, to form an FET with the drain being connected to an I/O pad which is subject to an ESD event. A resistive path extends through an opening in the conductive band region to a substrate contact, providing an increased I/O pad to substrate resistance which decreases the trigger voltage for the ESD NMOSFET.

摘要翻译： ESD NMOSFET，以及降低ESD NMOSFET触发电压的方法。 ESD NMOSFET配置在三阱CMOS结构中，其中第一阱通过相应的浅阱隔离区与第二阱和第三阱分离。 第一阱也通过导电带区沿着底部与衬底分离。 衬底触点位于第一，第二和第三阱的外部，并且在来自第一阱的ESD事件期间提供电流路径。 源极和漏极区域形成在第一阱中，以形成FET，其漏极连接到经受ESD事件的I / O焊盘。 电阻路径延伸穿过导电带区域中的开口到衬底接触，从而为衬底电阻提供增加的I / O焊盘，从而降低ESD NMOSFET的触发电压。