公开(公告)号：US08654579B2

公开(公告)日：2014-02-18

申请号：US13298591

申请日：2011-11-17

Applicant: Beom Yong Kim ,  Kwon Hong ,  Kee Jeung Lee ,  Ki Hong Lee

Inventor： Beom Yong Kim ,  Kwon Hong ,  Kee Jeung Lee ,  Ki Hong Lee

IPC: G11C11/40 ,  H01L29/792

CPC classification number: H01L27/11524 ,  G11C16/14 ,  G11C16/28 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

Abstract: A non-volatile memory device includes a plurality of memory cells stacked along a channel protruded from a substrate, a first select transistor connected to one end of the plurality of memory cells, a first interlayer dielectric layer for being coupled between a source line and the first select transistor, and a second interlayer dielectric layer disposed between the first select transistor and the one end of the plurality of memory cells, and configured to include a first recess region.

Abstract translation: 非易失性存储器件包括沿着从衬底突出的通道堆叠的多个存储器单元，连接到多个存储器单元的一端的第一选择晶体管，用于耦合在源极线与源极之间的第一层间电介质层 第一选择晶体管和设置在第一选择晶体管和多个存储单元的一端之间的第二层间电介质层，并且被配置为包括第一凹部区域。

公开(公告)号：US08319296B2

公开(公告)日：2012-11-27

申请号：US12648337

申请日：2009-12-29

Applicant: Kwan-Woo Do ,  Kee-Jeung Lee ,  Young-Dae Kim ,  Mi-Hyoung Lee ,  Jeong-Yeop Lee

Inventor： Kwan-Woo Do ,  Kee-Jeung Lee ,  Young-Dae Kim ,  Mi-Hyoung Lee ,  Jeong-Yeop Lee

IPC: H01L29/78 ,  H01L21/28

CPC classification number: C23C16/45531 ,  C23C16/34 ,  C23C16/36 ,  C23C16/4554 ,  H01L21/28537 ,  H01L21/28562 ,  H01L21/28568 ,  H01L27/10885 ,  H01L28/60 ,  H01L29/4966

Abstract: In a semiconductor device including a carbon-containing electrode and a method for fabricating the same, an electrode has a high work function due to a carbon-containing TiN layer contained therein. It is possible to provide a dielectric layer having a high permittivity and thus to reduce the leakage current by forming an electrode having a high work function. Also, sufficient capacitance of a capacitor can be secured by employing an electrode having a high work function and a dielectric layer having a high permittivity.

Abstract translation: 在包含含碳电极的半导体器件及其制造方法中，由于其中含有含碳的TiN层，电极具有高功函数。 可以提供具有高介电常数的介电层，从而通过形成具有高功函的电极来减小漏电流。 此外，通过使用具有高功函数的电极和具有高介电常数的电介质层，可以确保电容器的足够的电容。

公开(公告)号：US08288274B2

公开(公告)日：2012-10-16

申请号：US12318468

申请日：2008-12-30

Applicant: Deok-Sin Kil ,  Kee-Jeung Lee ,  Young-Dae Kim ,  Jin-Hyock Kim ,  Kwan-Woo Do ,  Kyung-Woong Park ,  Jeong-Yeop Lee ,  Ja-Yong Kim

Inventor： Deok-Sin Kil ,  Kee-Jeung Lee ,  Young-Dae Kim ,  Jin-Hyock Kim ,  Kwan-Woo Do ,  Kyung-Woong Park ,  Jeong-Yeop Lee ,  Ja-Yong Kim

IPC: H01L21/4763

CPC classification number: H01L21/28562 ,  C23C16/045 ,  C23C16/18 ,  C23C16/44 ,  C23C16/45525 ,  H01L21/28556 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76865 ,  H01L21/7687 ,  H01L21/76873 ,  H01L27/105 ,  H01L27/11502 ,  H01L28/65

Abstract: A noble metal layer is formed using ozone (O3) as a reaction gas.

Abstract translation: 使用臭氧（O 3）作为反应气体形成贵金属层。

公开(公告)号：US20120146196A1

公开(公告)日：2012-06-14

申请号：US13230973

申请日：2011-09-13

Applicant: Kee-Jeung LEE ,  Kwon Hong ,  Kyung-Woong Park ,  Ji-Hoon Ahn

Inventor： Kee-Jeung LEE ,  Kwon Hong ,  Kyung-Woong Park ,  Ji-Hoon Ahn

IPC: H01L29/02 ,  H01L21/328 ,  H01L21/314

CPC classification number: H01L21/02263 ,  C23C16/045 ,  C23C16/45529 ,  C23C16/45531 ,  C23C16/56 ,  H01L21/02148 ,  H01L21/02159 ,  H01L21/02161 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/02356 ,  H01L27/1085 ,  H01L28/40

Abstract: A semiconductor device includes a dielectric layer in which zirconium, hafnium, and a IV group element are mixed. A method for fabricating a capacitor includes forming a bottom electrode, forming the dielectric layer and forming a top electrode over the dielectric layer.

Abstract translation: 半导体器件包括其中混合有锆，铪和IV族元素的电介质层。 制造电容器的方法包括形成底电极，形成电介质层并在电介质层上形成顶电极。

公开(公告)号：US20120126308A1

公开(公告)日：2012-05-24

申请号：US13298591

申请日：2011-11-17

Applicant: Beom Yong KIM ,  Kwon HONG ,  Kee Jeung LEE ,  Ki Hong LEE

Inventor： Beom Yong KIM ,  Kwon HONG ,  Kee Jeung LEE ,  Ki Hong LEE

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L27/11524 ,  G11C16/14 ,  G11C16/28 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

Abstract: A non-volatile memory device includes a plurality of memory cells stacked along a channel protruded from a substrate, a first select transistor connected to one end of the plurality of memory cells, a first interlayer dielectric layer for being coupled between a source line and the first select transistor, and a second interlayer dielectric layer disposed between the first select transistor and the one end of the plurality of memory cells, and configured to include a first recess region.

Abstract translation: 非易失性存储器件包括沿着从衬底突出的通道堆叠的多个存储器单元，连接到多个存储器单元的一端的第一选择晶体管，用于耦合在源极线与源极之间的第一层间电介质层 第一选择晶体管和设置在第一选择晶体管和多个存储单元的一端之间的第二层间电介质层，并且被配置为包括第一凹部区域。

公开(公告)号：US08062943B2

公开(公告)日：2011-11-22

申请号：US12546603

申请日：2009-08-24

Applicant: Kee-jeung Lee

Inventor： Kee-jeung Lee

IPC: H01L21/8242

CPC classification number: H01L21/02189 ,  C23C16/0236 ,  C23C16/403 ,  C23C16/405 ,  C23C16/45525 ,  C23C16/45529 ,  C23C16/56 ,  H01L21/02178 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/3142 ,  H01L21/31616 ,  H01L21/31641 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/90 ,  Y02T50/67

Abstract: A capacitor with zirconium oxide and a method for fabricating the same are provided. The method includes: forming a storage node; forming a multi-layered dielectric structure on the storage node, the multi-layered dielectric structure including a zirconium oxide (ZrO2) layer and an aluminum oxide (Al2O3) layer; and forming a plate electrode on the multi-layered dielectric structure.

公开(公告)号：US08048757B2

公开(公告)日：2011-11-01

申请号：US13069290

申请日：2011-03-22

Applicant: Jae-Sung Roh ,  Kee-Jeung Lee ,  Han-Sang Song ,  Seung-Jin Yeom ,  Deok-Sin Kil ,  Young-Dae Kim ,  Jin-Hyock Kim

Inventor： Jae-Sung Roh ,  Kee-Jeung Lee ,  Han-Sang Song ,  Seung-Jin Yeom ,  Deok-Sin Kil ,  Young-Dae Kim ,  Jin-Hyock Kim

IPC: H01L21/20

CPC classification number: H01L28/91 ,  H01L27/10852 ,  H01L28/65

Abstract: A method for fabricating a capacitor includes forming an isolation layer over a cell region and a peripheral region of a substrate. The isolation layer forms a plurality of open regions in the cell region. Storage nodes are formed on surfaces of the open regions. An upper portion of the isolation layer is etched to expose upper outer walls of the storage nodes. A sacrificial pattern is formed over the isolation layer to enclose the upper outer walls of the storage nodes. The isolation layer in the peripheral region is etched to expose side portions of the resulting structure obtained after forming the sacrificial pattern in the cell region. With the sacrificial pattern supporting the storage nodes, the isolation layer in the cell region is removed. The sacrificial pattern is then removed.

Abstract translation: 制造电容器的方法包括在衬底的单元区域和周边区域上形成隔离层。 隔离层在单元区域中形成多个开放区域。 存储节点形成在开放区域的表面上。 蚀刻隔离层的上部以露出存储节点的上部外壁。 在隔离层上形成牺牲图案以封闭存储节点的上外壁。 对外围区域中的隔离层进行蚀刻，以在单元区域中形成牺牲图案之后获得的所得结构的侧面露出。 利用支持存储节点的牺牲图案，移除单元区域中的隔离层。 然后去除牺牲图案。

公开(公告)号：US20110171807A1

公开(公告)日：2011-07-14

申请号：US13069290

申请日：2011-03-22

Applicant: Jae-Sung Roh ,  Kee-Jeung Lee ,  Han-Sang Song ,  Seung-Jin Yeom ,  Deok-Sin Kil ,  Young-Dae Kim ,  Jin-Hyock Kim

Inventor： Jae-Sung Roh ,  Kee-Jeung Lee ,  Han-Sang Song ,  Seung-Jin Yeom ,  Deok-Sin Kil ,  Young-Dae Kim ,  Jin-Hyock Kim

IPC: H01L21/02

CPC classification number: H01L28/91 ,  H01L27/10852 ,  H01L28/65

Abstract: A method for fabricating a capacitor includes forming an isolation layer over a cell region and a peripheral region of a substrate. The isolation layer forms a plurality of open regions in the cell region. Storage nodes are formed on surfaces of the open regions. An upper portion of the isolation layer is etched to expose upper outer walls of the storage nodes. A sacrificial pattern is formed over the isolation layer to enclose the upper outer walls of the storage nodes. The isolation layer in the peripheral region is etched to expose side portions of the resulting structure obtained after forming the sacrificial pattern in the cell region. With the sacrificial pattern supporting the storage nodes, the isolation layer in the cell region is removed. The sacrificial pattern is then removed.

Abstract translation: 制造电容器的方法包括在衬底的单元区域和周边区域上形成隔离层。 隔离层在单元区域中形成多个开放区域。 存储节点形成在开放区域的表面上。 蚀刻隔离层的上部以露出存储节点的上部外壁。 在隔离层上形成牺牲图案以封闭存储节点的上外壁。 对外围区域中的隔离层进行蚀刻，以在单元区域中形成牺牲图案之后获得的所得结构的侧面露出。 利用支持存储节点的牺牲图案，移除单元区域中的隔离层。 然后去除牺牲图案。

公开(公告)号：US20110169134A1

公开(公告)日：2011-07-14

申请号：US13069280

申请日：2011-03-22

Applicant: Kee-Jeung Lee ,  Han-Sang Song ,  Deok-Sin Kil ,  Young-Dae Kim ,  Jin-Hyock Kim ,  Kwan-Woo Do ,  Kyung-Woong Park

Inventor： Kee-Jeung Lee ,  Han-Sang Song ,  Deok-Sin Kil ,  Young-Dae Kim ,  Jin-Hyock Kim ,  Kwan-Woo Do ,  Kyung-Woong Park

IPC: H01L29/02

CPC classification number: H01L28/65 ,  H01L27/10852 ,  H01L28/90

Abstract: A capacitor includes a pillar-type storage node, a supporter disposed entirely within an inner empty crevice of the storage node, a conductive capping layer over the supporter and contacting the storage node so as to seal an entrance to the inner empty crevice, a dielectric layer over the storage node, and a plate node over the dielectric layer.

Abstract translation: 一种电容器包括：柱状存储节点，完全位于存储节点的内部空缝隙内的支撑件，在支撑件上方的导电覆盖层，并与存储节点接触，以密封内部空缝隙的入口;电介质 存储节点上的平板节点以及电介质层上的平板节点。

公开(公告)号：US20100096609A1

公开(公告)日：2010-04-22

申请号：US12493672

申请日：2009-06-29

Applicant: Jin Hyock KIM ,  Kee Jeung LEE ,  Deok Sin KIL

Inventor： Jin Hyock KIM ,  Kee Jeung LEE ,  Deok Sin KIL

IPC: H01L47/00 ,  H01L21/00

CPC classification number: H01L45/143 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1616 ,  H01L45/1641

Abstract: A phase change memory device that has a layered phase change layer composed of multiple phase change materials is presented. The device includes a semiconductor substrate, an interlayer dielectric layer, a high-temperature crystallization phase change, a low-temperature crystallization phase change layer, and an upper electrode. The interlayer dielectric layer formed on the semiconductor substrate and the high-temperature crystallization phase change layer is formed on the interlayer dielectric layer. The low-temperature crystallization phase change layer is formed over the high-temperature crystallization phase change layer. The upper electrode is formed over the low-temperature crystallization phase change layer. An optional diffusion barrier may be interposed between the two phase change layers.

Abstract translation: 提出了具有由多个相变材料构成的分层相变层的相变存储器件。 该器件包括半导体衬底，层间介电层，高温结晶相变，低温结晶相变层和上电极。 形成在半导体衬底上的层间电介质层和高温结晶相变层形成在层间电介质层上。 在高温结晶相变层上形成低温结晶相变层。 上电极形成在低温结晶相变层上。 可以在两个相变层之间插入可选的扩散阻挡层。