公开(公告)号：US07560692B2

公开(公告)日：2009-07-14

申请号：US11617386

申请日：2006-12-28

申请人： Keith E. Barton ,  Steven H. Boettcher ,  John G. Gaudiello ,  Leon J. Kimball ,  Yun-Yu Wang

发明人： Keith E. Barton ,  Steven H. Boettcher ,  John G. Gaudiello ,  Leon J. Kimball ,  Yun-Yu Wang

IPC分类号： G01N1/32 ,  G01N23/04

CPC分类号： G01N1/2806

摘要： A high quality electron microscopy sample suitable for electron holography is prepared by forming markers filled with TEOS oxide and by repeatedly applying multiple coats of an adhesive followed by a relatively low temperature cure after each application. The TEOS oxide marker is readily visible during the polish, has a similar polish rate as a semiconductor material, and reduces contamination during sample preparation. The repeated application of adhesives separated by relatively low temperature cures increases the adhesive strength of the adhesive material to the semiconductor material without making it too brittle. This results in an improved control and yield of the sample preparation process.

摘要翻译： 适用于电子全息术的高品质电子显微镜样品通过形成填充有TEOS氧化物的标记物，并通过反复施加多层粘合剂，然后在每次涂布之后进行相对低温固化来制备。 TEOS氧化物标记在抛光期间容易看到，具有与半导体材料相似的抛光速率，并减少样品制备过程中的污染。 通过相对低温固化分离的粘合剂的重复施加增加了粘合剂材料对半导体材料的粘合强度，而不会使其变得太脆。 这导致样品制备过程的改进的控制和产率。

公开(公告)号：US07214935B2

公开(公告)日：2007-05-08

申请号：US10711690

申请日：2004-09-30

申请人： Thomas A. Bauer ,  Steven H. Boettcher ,  Anthony G. Domenicucci ,  John G. Gaudiello ,  Leon J. Kimball ,  Jeffrey S. McMurray ,  Yun-Yu Wang

发明人： Thomas A. Bauer ,  Steven H. Boettcher ,  Anthony G. Domenicucci ,  John G. Gaudiello ,  Leon J. Kimball ,  Jeffrey S. McMurray ,  Yun-Yu Wang

IPC分类号： G01N1/32 ,  G01N23/04

CPC分类号： G01N1/32 ,  G01N23/04 ,  H01J2237/2614

摘要： A method for preparing a transmission electron microscopy (TEM) sample for electron holography includes forming a sacrificial material over an area of interest on the sample, and polishing the sample to a desired thickness, wherein the area of interest is protected from rounding during the polishing. The sacrificial material is removed from the sample following the polishing.

摘要翻译： 制备用于电子全息术的透射电子显微镜（TEM）样品的方法包括在样品上的感兴趣区域上形成牺牲材料，并将样品抛光至所需厚度，其中在抛光过程中保护感兴趣区域免于四舍五入 。 抛光后，从样品中除去牺牲材料。

公开(公告)号：US06153935A

公开(公告)日：2000-11-28

申请号：US409244

申请日：1999-09-30

申请人： Daniel C. Edelstein ,  Timothy J. Dalton ,  John G. Gaudiello ,  Mahadevaiyer Krishnan ,  Sandra G. Malhotra ,  Maurice McGlashan-Powell ,  Eugene J. O'Sullivan ,  Carlos J. Sambucetti

发明人： Daniel C. Edelstein ,  Timothy J. Dalton ,  John G. Gaudiello ,  Mahadevaiyer Krishnan ,  Sandra G. Malhotra ,  Maurice McGlashan-Powell ,  Eugene J. O'Sullivan ,  Carlos J. Sambucetti

IPC分类号： H01L21/30 ,  H01L21/288 ,  H01L21/321 ,  H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76849 ,  H01L21/288 ,  H01L21/3212 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76835

摘要： A damascene interconnect containing a dual etch stop/diffusion barrier. The conductive material of the damascene interconnect is capped with a conductive metal diffusion barrier cap, typically using electroless deposition, and, optionally, with a dielectric etch-stop layer. An optional chemical mechanical polish-stop layer may also be present. The different methods of the invention allow the CMP stop, reactive-ion etch stop, and metal diffusion barrier requirements of the different layers to be decoupled. A preferred conductive material is copper.

摘要翻译： 包含双蚀刻停止/扩散屏障的镶嵌互连。 镶嵌互连的导电材料用导电金属扩散阻挡盖（通常使用无电沉积）和可选地与电介质蚀刻停止层封盖。 还可以存在任选的化学机械抛光 - 停止层。 本发明的不同方法允许不同层的CMP停止，反应离子蚀刻停止和金属扩散阻挡层要求被去耦合。 优选的导电材料是铜。

公开(公告)号：US20090001337A1

公开(公告)日：2009-01-01

申请号：US11771457

申请日：2007-06-29

申请人： Toshiharu Furukawa ,  John G. Gaudiello ,  Mark Charles Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles William Koburger, III ,  Chung Hon Lam

发明人： Toshiharu Furukawa ,  John G. Gaudiello ,  Mark Charles Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles William Koburger, III ,  Chung Hon Lam

IPC分类号： H01L21/336 ,  H01L21/06 ,  H01L29/02

CPC分类号： H01L45/06 ,  G11C13/0004 ,  H01L27/2454 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1683

摘要： A memory cell in an integrated circuit is fabricated in part by forming a lower electrode feature, an island, a sacrificial feature, a gate feature, and a phase change feature. The island is formed on the lower electrode feature and has one or more sidewalls. It comprises a lower doped feature, a middle doped feature formed above the lower doped feature, and an upper doped feature formed above the middle doped feature. The sacrificial feature is formed above the island, while the gate feature is formed along each sidewall of the island. The gate feature overlies at least a portion of the middle doped feature of the island and is operative to control an electrical resistance therein. Finally, the phase feature is formed above the island at least in part by replacing at least a portion of the sacrificial feature with a phase change material. The phase change material is operative to switch between lower and higher electrical resistance states in response to an application of an electrical signal.

摘要翻译： 部分地通过形成下电极特征，岛，牺牲特征，栅极特征和相变特征来制造集成电路中的存储单元。 岛形成在下电极特征上并具有一个或多个侧壁。 它包括下掺杂特征，形成在下掺杂特征之上的中掺杂特征，以及形成在中掺杂特征之上的上掺杂特征。 牺牲特征形成在岛上方，而栅极特征沿着岛的每个侧壁形成。 栅极特征覆盖岛的中间掺杂特征的至少一部分，并且可操作以控制其中的电阻。 最后，相位特征至少部分地通过用相变材料代替牺牲特征的至少一部分而在岛上方形成。 响应于电信号的应用，相变材料可操作以在较低和较高的电阻状态之间切换。

公开(公告)号：US06646345B2

公开(公告)日：2003-11-11

申请号：US09966629

申请日：2001-09-27

申请人： Carlos Juan Sambucetti ,  Judith Marie Rubino ,  Daniel Charles Edelstein ,  Cyryl Cabral, Jr. ,  George Frederick Walker ,  John G Gaudiello ,  Horatio Seymour Wildman

发明人： Carlos Juan Sambucetti ,  Judith Marie Rubino ,  Daniel Charles Edelstein ,  Cyryl Cabral, Jr. ,  George Frederick Walker ,  John G Gaudiello ,  Horatio Seymour Wildman

IPC分类号： H01L2348

CPC分类号： H01L21/76846 ,  C23C18/1651 ,  C23C18/1841 ,  C23C18/44 ,  C23C18/50 ,  H01L21/288 ,  H01L21/76849 ,  H01L21/76858 ,  H01L21/76864 ,  H01L21/76874 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a quaternary alloy film of Co—W—P—Au for use as a diffusion barrier layer on a copper interconnect in a semiconductor structure and devices formed incorporating such film are disclosed. In the method, a substrate that has copper conductive regions on top is first pre-treated by two separate pre-treatment steps. In the first step, the substrate is immersed in a H2SO4 rinsing solution and next in a solution containing palladium ions for a length of time sufficient for the ions to deposit on the surface of the copper conductive regions. The substrate is then immersed in a solution that contains at least 15 gr/l sodium citrate or EDTA for removing excess palladium ions from the surface of the copper conductive regions. After the pre-treated substrate is rinsed in a first rinsing step by distilled water, the substrate is electroless plated a Co—W—P film on the surfaces of the copper conductive regions in a first plating solution that contains cobalt ions, tungstate ions, citrate ions and a reducing agent. After the substrate coated with the Co—W—P film is rinsed in a second rinsing step by distilled water, the substrate is immersed in a second electroless plating solution for depositing a Au layer on top of the Co—W—P film. The present invention novel quaternary alloy film can be used as an effective diffusion barrier layer between a copper interconnect and silicon substrate or SiO2 dielectric layers.

公开(公告)号：US07699996B2

公开(公告)日：2010-04-20

申请号：US11680204

申请日：2007-02-28

申请人： Toshiharu Furukawa ,  John G. Gaudiello ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger, III

发明人： Toshiharu Furukawa ,  John G. Gaudiello ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger, III

IPC分类号： H01B13/00

CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28123

摘要： A method for simultaneously forming multiple line-widths, one of which is less than that achievable employing conventional lithographic techniques. The method includes providing a structure which includes a memory layer and a sidewall image transfer (SIT) layer on top of the memory layer. Then, the SIT layer is patterned resulting in a SIT region. Then, the SIT region is used as a blocking mask during directional etching of the memory layer resulting in a first memory region. Then, a side wall of the SIT region is retreated a retreating distance D in a reference direction resulting in a SIT portion. Said patterning comprises a lithographic process. The retreating distance D is less than a critical dimension CD associated with the lithographic process. The SIT region includes a first dimension W2 and a second dimension W3 in the reference direction, wherein CD

摘要翻译： 同时形成多个线宽的方法，其中之一小于使用常规光刻技术可实现的线宽。 该方法包括提供在存储层顶部包括存储层和侧壁图像传输（SIT）层的结构。 然后，对SIT层进行图案化，形成SIT区域。 然后，在存储层的定向蚀刻期间，将SIT区域用作阻挡掩模，产生第一存储区域。 然后，SIT区域的侧壁在参考方向上退回退避距离D，导致SIT部分。 所述图案化包括光刻工艺。 退回距离D小于与光刻工艺相关联的关键尺寸CD。 SIT区域包括参考方向上的第一维度W2和第二维度W3，其中CD

公开(公告)号：US06323128B1

公开(公告)日：2001-11-27

申请号：US09320499

申请日：1999-05-26

申请人： Carlos Juan Sambucetti ,  Judith Marie Rubino ,  Daniel Charles Edelstein ,  Cyryl Cabral, Jr. ,  George Frederick Walker ,  John G Gaudiello ,  Horatio Seymour Wildman

发明人： Carlos Juan Sambucetti ,  Judith Marie Rubino ,  Daniel Charles Edelstein ,  Cyryl Cabral, Jr. ,  George Frederick Walker ,  John G Gaudiello ,  Horatio Seymour Wildman

IPC分类号： H01L21441

CPC分类号： H01L21/76846 ,  C23C18/1651 ,  C23C18/1841 ,  C23C18/44 ,  C23C18/50 ,  H01L21/288 ,  H01L21/76849 ,  H01L21/76858 ,  H01L21/76864 ,  H01L21/76874 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a quaternary alloy film of Co—W—P—Au for use as a diffusion barrier layer on a copper interconnect in a semiconductor structure and devices formed incorporating such film are disclosed. In the method, a substrate that has copper conductive regions on top is first pre-treated by two separate pre-treatment steps. In the first step, the substrate is immersed in a H2SO4 rinsing solution and next in a solution containing palladium ions for a length of time sufficient for the ions to deposit on the surface of the copper conductive regions. The substrate is then immersed in a solution that contains at least 15 gr/l sodium citrate or EDTA for removing excess palladium ions from the surface of the copper conductive regions. After the pre-treated substrate is rinsed in a first rinsing step by distilled water, the substrate is electroless plated a Co—W—P film on the surfaces of the copper conductive regions in a first plating solution that contains cobalt ions, tungstate ions, citrate ions and a reducing agent. After the substrate coated with the Co—W—P film is rinsed in a second rinsing step by distilled water, the substrate is immersed in a second electroless plating solution for depositing a Au layer on top of the Co—W—P film. The present invention novel quaternary alloy film can be used as an effective diffusion barrier layer between a copper interconnect and silicon substrate or SiO2 dielectric layers.

摘要翻译： 公开了一种用于在半导体结构中的铜互连上用作扩散阻挡层的Co-W-P-Au的四元合金膜的形成方法和包含这种膜的器件。 在该方法中，首先通过两个单独的预处理步骤对具有铜导电区域的基板进行预处理。 在第一步骤中，将衬底浸入H 2 SO 4冲洗溶液中，接着在含有钯离子的溶液中浸渍一段足以使离子沉积在铜导电区域表面上的时间。 然后将基底浸入含有至少15g / l柠檬酸钠或EDTA的溶液中，以从铜导电区域的表面除去过量的钯离子。 在通过蒸馏水在第一冲洗步骤中冲洗预处理的基材之后，在包含钴离子，钨酸根离子，柠檬酸根离子的第一电镀液中，在铜导电区域的表面上化学镀Co-WP膜 和还原剂。 在用Co-W-P膜涂布的基材在第二次漂洗步骤中用蒸馏水冲洗后，将基板浸渍在Co-W-P膜顶部沉积Au层的第二无电镀液中。 本发明的新型四元合金膜可以用作铜互连和硅衬底或SiO 2电介质层之间的有效扩散阻挡层。

公开(公告)号：US07932167B2

公开(公告)日：2011-04-26

申请号：US11771457

申请日：2007-06-29

申请人： Toshiharu Furukawa ,  John G. Gaudiello ,  Mark Charles Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles William Koburger, III ,  Chung Hon Lam

发明人： Toshiharu Furukawa ,  John G. Gaudiello ,  Mark Charles Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles William Koburger, III ,  Chung Hon Lam

IPC分类号： H01L21/44

CPC分类号： H01L45/06 ,  G11C13/0004 ,  H01L27/2454 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1683

摘要： A memory cell in an integrated circuit is fabricated in part by forming a lower electrode feature, an island, a sacrificial feature, a gate feature, and a phase change feature. The island is formed on the lower electrode feature and has one or more sidewalls. It comprises a lower doped feature, a middle doped feature formed above the lower doped feature, and an upper doped feature formed above the middle doped feature. The sacrificial feature is formed above the island, while the gate feature is formed along each sidewall of the island. The gate feature overlies at least a portion of the middle doped feature of the island and is operative to control an electrical resistance therein. Finally, the phase feature is formed above the island at least in part by replacing at least a portion of the sacrificial feature with a phase change material. The phase change material is operative to switch between lower and higher electrical resistance states in response to an application of an electrical signal.

摘要翻译： 部分地通过形成下电极特征，岛，牺牲特征，栅极特征和相变特征来制造集成电路中的存储单元。 岛形成在下电极特征上并具有一个或多个侧壁。 它包括下掺杂特征，形成在下掺杂特征之上的中掺杂特征，以及形成在中掺杂特征之上的上掺杂特征。 牺牲特征形成在岛上方，而栅极特征沿着岛的每个侧壁形成。 栅极特征覆盖岛的中间掺杂特征的至少一部分，并且可操作以控制其中的电阻。 最后，相位特征至少部分地通过用相变材料代替牺牲特征的至少一部分而在岛上方形成。 响应于电信号的应用，相变材料可操作以在较低和较高的电阻状态之间切换。

公开(公告)号：US20080206996A1

公开(公告)日：2008-08-28

申请号：US11680204

申请日：2007-02-28

申请人： Toshiharu Furukawa ,  John G. Gaudiello ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger

发明人： Toshiharu Furukawa ,  John G. Gaudiello ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger

IPC分类号： H01L21/302

CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28123

摘要： A method for simultaneously forming multiple line-widths, one of which is less than that achievable employing conventional lithographic techniques. The method includes providing a structure which includes a memory layer and a sidewall image transfer (SIT) layer on top of the memory layer. Then, the SIT layer is patterned resulting in a SIT region. Then, the SIT region is used as a blocking mask during directional etching of the memory layer resulting in a first memory region. Then, a side wall of the SIT region is retreated a retreating distance D in a reference direction resulting in a SIT portion. Said patterning comprises a lithographic process. The retreating distance D is less than a critical dimension CD associated with the lithographic process. The SIT region includes a first dimension W2 and a second dimension W3 in the reference direction, wherein CD

摘要翻译： 同时形成多个线宽的方法，其中之一小于使用常规光刻技术可实现的线宽。 该方法包括提供在存储层顶部包括存储层和侧壁图像传输（SIT）层的结构。 然后，对SIT层进行图案化，形成SIT区域。 然后，在存储层的定向蚀刻期间，将SIT区域用作阻挡掩模，产生第一存储区域。 然后，SIT区域的侧壁在参考方向上退回退避距离D，导致SIT部分。 所述图案化包括光刻工艺。 退回距离D小于与光刻工艺相关联的关键尺寸CD。 SIT区域包括参考方向上的第一维W 2和第二维W 3，其中CD

公开(公告)号：US20080156987A1

公开(公告)日：2008-07-03

申请号：US11617386

申请日：2006-12-28

申请人： Keith E. Barton ,  Steven H. Boettcher ,  John G. Gaudiello ,  Leon J. Kimball ,  Yun Yu Wang

发明人： Keith E. Barton ,  Steven H. Boettcher ,  John G. Gaudiello ,  Leon J. Kimball ,  Yun Yu Wang

IPC分类号： G01N23/04

CPC分类号： G01N1/2806

摘要： A high quality electron microscopy sample suitable for electron holography is prepared by forming markers filled with TEOS oxide and by repeatedly applying multiple coats of an adhesive followed by a relatively low temperature cure after each application. TEOS oxide marker is readily visible during the polish, has a similar polish rate as semiconductor material, and reduces contamination during the sample preparation. The repeated application of adhesives separated by relatively low temperature cures increases the adhesive strength of the adhesive material to the semiconductor material without making it too brittle. This results in an improved control and yield of the sample preparation process.

摘要翻译： 适用于电子全息术的高品质电子显微镜样品通过形成填充有TEOS氧化物的标记物，并通过反复施加多层粘合剂，然后在每次涂布之后进行相对低温固化来制备。 TEOS氧化物标记在抛光期间容易看到，具有与半导体材料相似的抛光速率，并且减少样品制备过程中的污染。 通过相对低温固化分离的粘合剂的重复施加增加了粘合剂材料对半导体材料的粘合强度，而不会使其变得太脆。 这导致样品制备过程的改进的控制和产率。