公开(公告)号：US08201112B2

公开(公告)日：2012-06-12

申请号：US12129522

申请日：2008-05-29

申请人： David William Boerstler ,  Jieming Qi

发明人： David William Boerstler ,  Jieming Qi

IPC分类号： G06F17/50

CPC分类号： H03H11/405 ,  H03H11/1217

摘要： A design structure of a circuit for managing voltage swings across FETs comprising a reference precision resistor, a first and second FET, wherein a gate of the first FET is tied to a gate of the second FET, wherein a drain to source resistance of the second FET is substantially equal to or is a multiple of a resistance of the reference precision resistor, and wherein a gate voltage of the second FET is applied to a gate of the first FET to set a bias point of the first FET, and a third FET cascoded to the first FET, wherein a source of the first FET is coupled to the drain of the third FET to extend a voltage range in which respective gate voltages of the first and third FETs maintain a linear relationship with respective drain to source voltages of the first and third FETs.

摘要翻译： 一种用于管理跨FET的电压摆动的电路的设计结构，包括参考精密电阻器，第一和第二FET，其中第一FET的栅极连接到第二FET的栅极，其中第二FET的漏极 - 源极电阻 FET基本上等于或者是参考精密电阻器的电阻的倍数，并且其中第二FET的栅极电压被施加到第一FET的栅极以设置第一FET的偏置点，并且第三FET 级联到第一FET，其中第一FET的源极耦合到第三FET的漏极，以扩展电压范围，其中第一和第三FET的相应栅极电压与相应的漏极到源极电压保持线性关系 第一和第三FET。

公开(公告)号：US08037431B2

公开(公告)日：2011-10-11

申请号：US12126076

申请日：2008-05-23

申请人： David W. Boerstler ,  Eskinder Hailu ,  Jieming Qi ,  Mike Shen

发明人： David W. Boerstler ,  Eskinder Hailu ,  Jieming Qi ,  Mike Shen

IPC分类号： G06F17/50 ,  H03K3/03

CPC分类号： H03L7/0995 ,  H03K3/0315 ,  H03K5/133

摘要： A design structure embodied in a machine readable medium used in a design process includes an interleaved voltage-controlled oscillator, including a ring circuit of main logic inverter gates; a plurality of delay elements connected in parallel with a selected sequence of the main logic inverter gates; wherein each delay element comprises a feedforward section, comprising controls for regulating signal transmission through feedforward elements responsive to one or more control voltages; and a proportional section for regulating signal transmission through at least one logic inverter gate; at least one temperature compensation circuit responsive to a compensating voltage input that is proportional to temperature; an electronic circuit in communication with the temperature compensation circuit and configured to provide a voltage signal responsive to temperature; an amplifier in connection with the electronic circuit to amplify the voltage signal; and a DC offset generator configured to adjust the voltage of the amplified voltage signal.

摘要翻译： 体现在设计过程中使用的机器可读介质中的设计结构包括交错压控振荡器，包括主逻辑逆变器门的环形电路; 多个延迟元件，与所述主逻辑反相器门的选定序列并联连接; 其中每个延迟元件包括前馈部分，其包括用于响应于一个或多个控制电压来调节通过前馈元件的信号传输的控制; 以及用于调节通过至少一个逻辑反相器门的信号传输的比例部分; 响应于与温度成比例的补偿电压输入的至少一个温度补偿电路; 与所述温度补偿电路通信并且被配置为提供响应于温度的电压信号的电子电路; 与电子电路相连的放大器，用于放大电压信号; 以及配置成调整放大的电压信号的电压的DC偏移发生器。

公开(公告)号：US07747892B2

公开(公告)日：2010-06-29

申请号：US12036936

申请日：2008-02-25

申请人： David William Boerstler ,  Eskinder Hailu ,  Kazuhiko Miki ,  Jieming Qi

发明人： David William Boerstler ,  Eskinder Hailu ,  Kazuhiko Miki ,  Jieming Qi

IPC分类号： G06F1/04

CPC分类号： H03K19/017581 ,  H03K19/00323 ,  H03K19/00346

摘要： The present invention provides for a system comprising a level shifter configured to receive a first clock signal from a first power domain, to receive a counter signal, to select one of a plurality of intermediate voltages in response to the received counter signal, and to generate a second clock signal in response to the received first clock signal and the selected intermediate voltage. A counter is coupled to the level shifter and configured to receive a divided clock signal and a comparison result signal, and to generate the counter signal in response to the received divided clock signal and comparison result signal. A divider is coupled to the counter and configured to receive the first clock signal and to generate the divided clock signal in response to the received first clock signal. A filter is coupled to the level shifter and configured to receive the second clock signal and to generate a first comparison signal in response to the received second clock signal. A fixed potential is configured to generate a second comparison signal. A comparator is coupled to the filter, the fixed potential, and the counter and configured to receive the first comparison signal and the second comparison signal, and to generate the comparison result signal in response to the received first comparison signal and the second comparison signal.

摘要翻译： 本发明提供了一种系统，包括电平移位器，其被配置为从第一功率域接收第一时钟信号，以接收计数器信号，以响应于所接收的计数器信号选择多个中间电压中的一个，并产生 响应于所接收的第一时钟信号和所选择的中间电压的第二时钟信号。 计数器耦合到电平移位器并被配置为接收分频时钟信号和比较结果信号，并且响应于接收到的分频时钟信号和比较结果信号产生计数器信号。 分频器耦合到计数器并且被配置为接收第一时钟信号并响应于接收到的第一时钟信号产生分频时钟信号。 滤波器耦合到电平移位器并且被配置为接收第二时钟信号并响应于所接收的第二时钟信号产生第一比较信号。 固定电位被配置为产生第二比较信号。 比较器耦合到滤波器，固定电位和计数器，并且被配置为接收第一比较信号和第二比较信号，并且响应于接收的第一比较信号和第二比较信号产生比较结果信号。

公开(公告)号：US07737794B2

公开(公告)日：2010-06-15

申请号：US12120331

申请日：2008-05-14

申请人： David W. Boerstler ,  Masaaki Kaneko ,  Toshiyuki Ogata ,  Jieming Qi

发明人： David W. Boerstler ,  Masaaki Kaneko ,  Toshiyuki Ogata ,  Jieming Qi

IPC分类号： G01R23/02

CPC分类号： H03L1/022 ,  H03L1/00 ,  H03L7/099 ,  H03L2207/06

摘要： Mechanisms are provided for compensating for process and temperature variations in a circuit. The mechanisms may select at least one resistor in a plurality of resistors in the circuit to provide a resistance value for generating a calibration voltage input to the circuit to compensate for variations in process. A reference signal may be compared to a feedback signal generated by the circuit based on the calibration signal. A determination is made as to whether the feedback signal is within a tolerance of the reference signal and, if so, an identifier of the selected at least one resistor is stored in a memory device coupled to the circuit. The circuit may be operated using the selected at least one resistor based on the identifier stored in the memory device. An apparatus and integrated circuit device utilizing these mechanisms are also provided.

摘要翻译： 提供用于补偿电路中的工艺和温度变化的机构。 这些机构可以选择电路中的多个电阻器中的至少一个电阻器，以提供用于产生输入到电路的校准电压的电阻值，以补偿过程中的变化。 参考信号可以与基于校准信号的电路产生的反馈信号进行比较。 确定反馈信号是否在参考信号的公差之内，如果是，则将所选择的至少一个电阻器的标识符存储在耦合到该电路的存储器件中。 可以基于存储在存储器件中的标识符，使用所选择的至少一个电阻器来操作该电路。 还提供了利用这些机构的装置和集成电路装置。

公开(公告)号：US07716516B2

公开(公告)日：2010-05-11

申请号：US11471819

申请日：2006-06-21

申请人： Yosuke Muraki ,  Tetsuji Tamura ,  Iwao Takiguchi ,  Makoto Aikawa ,  Eskinder Hailu ,  Byron Lee Krauter ,  Stephen Douglas Weitzel ,  Jieming Qi ,  Kazuhiko Miki ,  David William Boerstler ,  Gilles Gervais ,  Kirk David Peterson ,  Robert Walter Berry, Jr. ,  Sang Hoo Dhong

发明人： Yosuke Muraki ,  Tetsuji Tamura ,  Iwao Takiguchi ,  Makoto Aikawa ,  Eskinder Hailu ,  Byron Lee Krauter ,  Stephen Douglas Weitzel ,  Jieming Qi ,  Kazuhiko Miki ,  David William Boerstler ,  Gilles Gervais ,  Kirk David Peterson ,  Robert Walter Berry, Jr. ,  Sang Hoo Dhong

IPC分类号： G06F1/04 ,  G06F1/24 ,  G06F11/00

CPC分类号： G06F1/04

摘要： A technology for supplying a power supply voltage to a microprocessor. Before normal arithmetic processing of the microprocessor, duty cycle correction process for adjusting the duty cycle of a clock signal inside the microprocessor is performed. In the duty cycle correction process for adjusting the duty cycle, the duty cycle of the clock signal is adjusted so as to minimize the power voltage at which the microprocessor is still operable.

摘要翻译： 用于向微处理器提供电源电压的技术。 在微处理器的正常运算处理之前，执行用于调整微处理器内的时钟信号占空比的占空比校正处理。 在用于调整占空比的占空比校正处理中，调整时钟信号的占空比以使微处理器仍然可操作的电源电压最小化。

公开(公告)号：US07595675B2

公开(公告)日：2009-09-29

申请号：US11381031

申请日：2006-05-01

申请人： David William Boerstler ,  Eskinder Hailu ,  Jieming Qi

发明人： David William Boerstler ,  Eskinder Hailu ,  Jieming Qi

IPC分类号： H03K5/04

CPC分类号： G01R31/31727

摘要： The disclosed methodology and apparatus measure the duty cycle of a reference clock signal that a clock circuit supplies to a duty cycle measurement (DCM) circuit. In one embodiment, the DCM circuit includes a capacitor driven by a charge pump. The reference clock signal drives the charge pump. The clock circuit varies the duty cycle of the reference clock signal among a number of known duty cycle values. The DCM circuit stores resultant capacitor voltage values corresponding to each of the known duty cycle values in a data store. The DCM circuit applies a test clock signal having an unknown duty cycle to the capacitor via the charge pump, thus charging the capacitor to a new voltage value that corresponds to the duty cycle of the test clock signal. Control software accesses the data store to determine the duty cycle to which the test clock signal corresponds.

摘要翻译： 所公开的方法和装置测量时钟电路提供给占空比测量（DCM）电路的参考时钟信号的占空比。 在一个实施例中，DCM电路包括由电荷泵驱动的电容器。 参考时钟信号驱动电荷泵。 时钟电路在多个已知的占空比值之间改变参考时钟信号的占空比。 DCM电路将对应于每个已知占空比值的合成电容电压值存储在数据存储器中。 DCM电路通过电荷泵向电容器施加具有未知占空比的测试时钟信号，从而将电容器充电到对应于测试时钟信号占空比的新电压值。 控制软件访问数据存储，以确定测试时钟信号对应的占空比。

公开(公告)号：US07589575B2

公开(公告)日：2009-09-15

申请号：US11877710

申请日：2007-10-24

申请人： David William Boerstler ,  Jieming Qi

发明人： David William Boerstler ,  Jieming Qi

IPC分类号： H03L7/06

CPC分类号： H03H11/245

摘要： A loop filter in a phase lock loop circuit comprising a reference precision resistor, a first FET and a second FET, wherein the gate of the first FET is tied to the gate of the second FET, and a filter capacitor connected to the first FET for producing a capacitor voltage. The capacitor voltage is applied to the source of the first FET, the source of the second FET, and to the bottom of the reference precision resistor acting as a virtual ground. The capacitor voltage generated by the filter capacitor sets the bias point of the second FET such that the second FET comprises characteristics of an integrated precision resistor. A predetermined voltage generated by the second FET is applied to the gate of the first FET to set the bias point of the first FET such that the first FET comprises characteristics of an integrated precision resistor.

摘要翻译： 一种锁相环电路中的环路滤波器，包括参考精密电阻器，第一FET和第二FET，其中第一FET的栅极连接到第二FET的栅极，以及连接到第一FET的滤波电容器， 产生电容电压。 电容器电压施加到第一FET的源极，第二FET的源极和作为虚拟接地的参考精密电阻的底部。 由滤波电容产生的电容器电压设定第二FET的偏置点，使得第二FET包括集成精密电阻器的特性。 将由第二FET产生的预定电压施加到第一FET的栅极，以设置第一FET的偏置点，使得第一FET包括集成精密电阻器的特性。

公开(公告)号：US20090132971A1

公开(公告)日：2009-05-21

申请号：US12130040

申请日：2008-05-30

申请人： David W. Boerstler ,  Eskinder Hailu ,  Masaaki Kaneko ,  Jieming Qi

发明人： David W. Boerstler ,  Eskinder Hailu ,  Masaaki Kaneko ,  Jieming Qi

IPC分类号： H03B19/00 ,  G06F17/50

CPC分类号： G06F17/5045 ,  H03K3/017 ,  H03L7/0995 ,  H03L2207/06

摘要： A design structure for a circuit for obtaining a desired phase locked loop (PLL) duty cycle without a pre-scaler is provided. The PLL circuit of the illustrative embodiments utilizes two separate loops that simultaneously operate on the VCO. One loop ensures the frequency and phase lock while the other loop ensures the duty cycle lock. The VCO is modified to have an additional control port to adjust the duty cycle. Thus, the VCO has one control port for performing frequency adjustment and one control port for duty cycle adjustment. As a result, both the duty cycle and the frequency may be controlled using the VCO of the PLL circuit of the illustrative embodiments so as to achieve any desired duty cycle output without requiring a VCO pre-scaler circuit or duty cycle correction circuit.

摘要翻译： 提供了一种用于在没有预定标器的情况下获得期望的锁相环（PLL）占空比的电路的设计结构。 说明性实施例的PLL电路利用在VCO上同时工作的两个单独的环路。 一个环路确保频率和相位锁定，而另一个环路确保占空比锁定。 VCO被修改为具有附加的控制端口来调整占空比。 因此，VCO具有用于执行频率调整的一个控制端口和用于占空比调整的一个控制端口。 结果，可以使用说明性实施例的PLL电路的VCO来控制占空比和频率，以便实现任何期望的占空比输出，而不需要VCO预定标器电路或占空比校正电路。

公开(公告)号：US20090108923A1

公开(公告)日：2009-04-30

申请号：US12129514

申请日：2008-05-29

申请人： David William Boerstler ,  Jieming Qi

发明人： David William Boerstler ,  Jieming Qi

IPC分类号： G05F1/10 ,  G06F17/50

CPC分类号： H03H11/245

摘要： A design structure for a loop filter in a phase lock loop circuit comprising a reference precision resistor, a first and second FET, wherein the gate of the first FET is tied to the gate of the second FET, and a filter capacitor connected to the first FET for producing a capacitor voltage. The capacitor voltage is applied to the source of the first FET, the source of the second FET, and the bottom of the reference precision resistor acting as a virtual ground. The capacitor voltage generated by the filter capacitor sets the bias point of the second FET such that the second FET comprises characteristics of an integrated precision resistor. A predetermined voltage generated by the second FET is applied to the gate of the first FET to set the bias point of the first FET such that the first FET comprises characteristics of an integrated precision resistor.

摘要翻译： 一种锁相环电路中的环路滤波器的设计结构，包括参考精密电阻器，第一和第二FET，其中第一FET的栅极连接到第二FET的栅极，以及连接到第一FET的滤波电容器 用于产生电容器电压的FET。 电容器电压施加到第一FET的源极，第二FET的源极和参考精密电阻的底部作为虚拟接地。 由滤波电容产生的电容器电压设定第二FET的偏置点，使得第二FET包括集成精密电阻器的特性。 将由第二FET产生的预定电压施加到第一FET的栅极，以设置第一FET的偏置点，使得第一FET包括集成精密电阻器的特性。

公开(公告)号：US07511554B2

公开(公告)日：2009-03-31

申请号：US11764262

申请日：2007-06-18

申请人： Masaaki Kaneko ,  David W. Boerstler ,  Eskinder Hailu ,  Jieming Qi

发明人： Masaaki Kaneko ,  David W. Boerstler ,  Eskinder Hailu ,  Jieming Qi

IPC分类号： H03L5/00

CPC分类号： H03K19/01812 ,  H03K19/01831

摘要： Systems and methods for conveying signals between integrated circuit (IC) components in domains having different supply voltages. AC coupling is used to increase the speed at which the common mode voltage of a signal is shifted from one level to another. One embodiment comprises a method for level shifting a binary signal in an IC. This method includes receiving an input binary signal and decoupling its AC component from its common mode component. A second common mode component is added to the AC component, providing a binary output signal. The common mode voltage of the input signal may be greater (or smaller) than that of the output signal. In one embodiment of the method, duty cycle compensation (DCC) is performed. The DCC drives the duty cycle toward a desired value.

摘要翻译： 在具有不同电源电压的域中的集成电路（IC）组件之间传送信号的系统和方法。 AC耦合用于增加信号的共模电压从一个电平转移到另一个电平的速度。 一个实施例包括用于电平移位IC中的二进制信号的方法。 该方法包括接收输入二进制信号并将其AC分量与其共模分量去耦。 第二共模分量被添加到AC分量，提供二进制输出信号。 输入信号的共模电压可以大于（或更小）输出信号的共模电压。 在该方法的一个实施例中，执行占空比补偿（DCC）。 DCC将占空比驱动到所需的值。